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| mixed signal isp flash mcu family c8051f040/1/2/3/4/5/6/7 rev. 1.5 12/05 copyright ? 2005 by silicon laboratories c8051f04x analog peripherals - 10 or 12-bit sar adc ? 12-bit (c8051f040/1) or ? 10-bit (c8051f042/3/4/5/6/7) resolution ? 1 lsb inl, guaranteed no missing codes ? progr ammable throughput up to 100 ksps ? 13 external input s; single-ended or differential ? sw progr ammable high voltage difference amplifier ? progr ammable amplifier gain: 16, 8, 4, 2, 1, 0.5 ? dat a-dependent windowed interrupt generator ? built-in temper ature sensor - 8-bit sar adc (c8051f040/1/2/3 only) ? programmable throughput up to 500 ksps ? 8 ext ernal inputs, si ngle-ended or differential ? progr ammable amplifier gain: 4, 2, 1, 0.5 - two 12-bit dacs (c8051f040/1/2/3 only) ? can synchronize outputs to timers for jitter-free wave - form generation - three analog comparators ? programmable hysteresis/response time - voltage reference - precision v dd monitor/brown-out detector on-chip jtag debug & boundary scan - on-chip debug circuitry facilitates full- speed, non- intrusive in-circuit/in-system debugging - provides breakpoints, single-stepping, watchpoints, stack monitor; inspect/modi fy memory and registers - superior performance to emulation systems using ice-chips, target pods, and sockets - ieee1149.1 compli ant boundary scan - complete development kit high-speed 8051 c core - pipelined instruction architecture; executes 70% of instruction set in 1 or 2 system clocks - up to 25 mips throughput with 25 mhz clock - 20 vectored interrupt sources memory - 4352 bytes internal data ram (4 k + 256) - 64 kb (c8051f040/1/2/3/4/5) ? or 32 kb (c8051f046/7) flash; in-system program - mable in 512-byte sectors - external 64 kb data memory interface (programma - ble multiplexed or non-multiplexed modes) digital peripherals - 8 byte-wide port i/o (c8051f040/2/4/6); 5 v tolerant - 4 byte-wide port i/o (c8051f041/3/5/7); 5 v tolerant - bosch controller area network (can 2.0b), hard - ware smbus? (i 2 c? compatible), spi?, and two uart serial ports available concurrently - programmable 16-bit coun ter/timer array with 6 capture/compare modules - 5 general purpose 16-bit counter/timers - dedicated watch-dog timer; bi-directional reset pin clock sources - internal calibrated programmable oscillator: 3 to 24 .5 mhz - external oscillator: crystal, rc, c, or clock - real-time clock mode using timer 2, 3, 4, or pca supply voltage: 2.7 to 3.6 v - multiple power saving sleep and shutdown modes 100-pin and 64-pin tqfp packages available - temperature range: ?40 to +85 c jtag 64 kb/32 kb isp flash 4352 b sram sanity control + - 12/10-bit 100 ksps adc clock circuit pga vref 12-bit dac temp sensor voltage comparators analog peripherals port 0 port 1 port 2 port 3 crossbar digital i/o high-speed controller core debug circuitry 20 interrupts 8051 cpu (25 mips) + - 8-bit 500 ksps adc port 4 port 5 port 6 port 7 external memory interface 100 pin 64 pin pga uart0 smbus spi bus pca timer 0 timer 1 timer 2 timer 3 timer 4 uart1 amux amux can 2.0b + - hv diff amp 12-bit dac c8051f041/2/3 only
c8051f040/1/2/3/4/5/6/7 2 rev. 1.5 c8051f040/1/2/3/4/5/6/7 rev. 1.5 3 table of contents 1. system overview............ ............................................................................. ........... 19 1.1. cip-51? microcontroller core.. ............................................................. ........... 25 1.1.1. fully 8051 compatible...... ............................................................. ........... 25 1.1.2. improved throughput ............ ........................................................ ........... 25 1.1.3. additional features .......... ............................................................. ........... 26 1.2. on-chip memory......... ........................................................................... ........... 27 1.3. jtag debug and boundary scan.. ........................................................ ........... 28 1.4. programmable digital i/o and crossbar ............... ................................. ........... 29 1.5. programmable counter array ... ............................................................. ........... 30 1.6. controller area network.......... ............................................................... ........... 31 1.7. serial ports ............ ................................................................................ ........... 31 1.8. 12/10-bit analog to digital c onverter.................. ................................. ............. 32 1.9. 8-bit analog to digital converter (c8051f040/1/2/3 only ) .................. ............. 33 1.10.comparators and dacs ........... ............................................................. ........... 34 2. absolute maximum ratings ........ ............................................................... ........... 35 3. global dc electrical characteristi c ........................................................... ........... 36 4. pinout and package definitions..... ............... ............................................. ........... 37 5. 12-bit adc (adc 0, c8051f040/1 only) ....... ............................................... ........... 47 5.1. analog multiplexer and pga..... ............................................................. ........... 47 5.1.1. analog input configuration. ........................................................... ........... 48 5.2. high-voltage difference amplifier................ .......................................... ........... 52 5.3. adc modes of operation........ ............................................................... ........... 54 5.3.1. starting a conversion....... ............................................................. ........... 54 5.3.2. tracking modes................ ............................................................. ........... 54 5.3.3. settling time r equirements ................ .......................................... ........... 56 5.4. adc0 programmable window de tector ............... ................................. ........... 62 6. 10-bit adc (adc 0, c8051f042/3/4/5/6/7 only)........... ............................... ........... 69 6.1. analog multiplexer and pga..... ............................................................. ........... 69 6.1.1. analog input configuration. ........................................................... ........... 70 6.2. high-voltage difference amplifier................ .......................................... ........... 74 6.3. adc modes of operation........ ............................................................... ........... 76 6.3.1. starting a conversion....... ............................................................. ........... 76 6.3.2. tracking modes................ ............................................................. ........... 76 6.3.3. settling time r equirements ................ .......................................... ........... 78 6.4. adc0 programmable window de tector ............... ................................. ........... 84 7. 8-bit adc (adc2, c80 51f040/1/2/3 only) .......... .......................................... ......... 91 7.1. analog multiplexer and pga..... ............................................................. ........... 91 7.2. adc2 modes of operation...... ............................................................... ........... 92 7.2.1. starting a conversion....... ............................................................. ........... 92 7.2.2. tracking modes................ ............................................................. ........... 92 7.2.3. settling time r equirements ................ .......................................... ........... 94 7.3. adc2 programmable window de tector ............... ................................. ......... 100 7.3.1. window detector in singl e-ended mode........... ............................ ......... 100 c8051f040/1/2/3/4/5/6/7 4 rev. 1.5 7.3.2. window detector in differ ential mode .......... ................................. ......... 102 8. dacs, 12-bit voltage mode (c8051f040/1/2/3 only) ........ ............... .................. 105 8.1. dac output scheduling ......................................................................... ......... 106 8.1.1. update output on-demand .. ........................................................ ......... 106 8.1.2. update output based on timer overflow ............. ............... .................. 106 8.2. dac output scaling/justificat ion ................. .......................................... ......... 106 9. voltage reference (c8051f040/2/4 /6) ........................................................ ......... 113 10. voltage reference (c8051f041/3/5 /7) ........................................................ ......... 117 11. comparators ................ ................................................................................ ......... 121 11.1.comparator inputs...... ........................................................................... ......... 123 12. cip-51 microcontroller .............. .................................................................. ......... 127 12.1.instruction set........... ............................................................................. ......... 129 12.1.1.instruction and cpu timing .. ........................................................ ......... 129 12.1.2.movx instruction and pr ogram memory .......... ............................ ......... 129 12.2.memory organization ............. ............................................................... ......... 133 12.2.1.program memory .... ...................................................................... ......... 133 12.2.2.data memory........ ......................................................................... ......... 134 12.2.3.general purpose registers ........................................................... ......... 134 12.2.4.bit addressable locations.. ........................................................... ......... 134 12.2.5.stack ............ ................................................................................ ......... 134 12.2.6.special function register s ........................................................... ......... 135 12.2.7.register description s ................ .................................................. ........... 150 12.3.interrupt handler....... ............................................................................. ......... 153 12.3.1.mcu interrupt sources and vectors ....... .............. ............... .................. 153 12.3.2.external interrupts.......... ............................................................... ......... 154 12.3.3.interrupt priorities........ .................................................................. ......... 156 12.3.4.interrupt latency .............. ............................................................. ......... 156 12.3.5.interrupt register descriptions............ .......................................... ......... 156 12.4.power management modes........ ........................................................... ......... 163 12.4.1.idle mode ........... ........................................................................... ......... 163 12.4.2.stop mode............ ......................................................................... ......... 164 13. reset sources.......... .................................................................................. ........... 165 13.1.power-on reset ....... ............................................................................. ......... 166 13.2.power-fail reset ........ ........................................................................... ......... 166 13.3.external reset .......... ............................................................................. ......... 166 13.4.missing clock detector reset ... ............... ............................................. ......... 167 13.5.comparator0 reset ............. .................................................................. ......... 167 13.6.external cnvstr0 pin reset ... ............... ............................................. ......... 167 13.7.watchdog timer reset.... ...................................................................... ......... 167 13.7.1.enable/reset wdt ............ ........................................................... ......... 168 13.7.2.disable wdt ........... ...................................................................... ......... 168 13.7.3.disable wdt lockout ............... .................................................. ........... 168 13.7.4.setting wdt interval ........ ............................................................. ......... 168 14. oscillators ................ .................................................................................. ........... 173 14.1.programmable internal oscilla tor .................... .............. ............... .................. 173 c8051f040/1/2/3/4/5/6/7 rev. 1.5 5 14.2.external oscillator drive circuit................ ............................................. ......... 175 14.3.system clock selectio n......................................................................... ......... 175 14.4.external crystal example .... .................................................................. ......... 177 14.5.external rc example .......... .................................................................. ......... 178 14.6.external capacitor example ... ............................................................... ......... 178 15. flash memory ................. ............................................................................. ......... 179 15.1.programming the flash memory .......................................................... ......... 179 15.2.non-volatile data storage ... .................................................................. ......... 180 15.3.security options ....... ............................................................................. ......... 180 15.3.1.summary of flash security options............. ................................. ......... 183 16. external data memory interface and on-chi p xram............ ................. ........... 187 16.1.accessing xram.......... ......................................................................... ......... 187 16.1.1.16-bit movx example ....... ........................................................... ......... 187 16.1.2.8-bit movx example ......... ........................................................... ......... 187 16.2.configuring the exte rnal memory interface . .......................................... ......... 188 16.3.port selection and c onfiguration.......... ................................................. ......... 188 16.4.multiplexed and non-multiplex ed selection.......... ................................. ......... 191 16.4.1.multiplexed configuration. ............................................................. ......... 191 16.4.2.non-multiplexed configurat ion.............. ................................................. 192 16.5.memory mode selection...... .................................................................. ......... 193 16.5.1.internal xram only ......... ............................................................. ......... 193 16.5.2.split mode without bank select............. ................................................. 193 16.5.3.split mode with ba nk select................ .......................................... ......... 194 16.5.4.external only...... ........................................................................... ......... 194 16.6.timing ............. .................................................................................. ........... 194 16.6.1.non-multiplexed mode ....... ........................................................... ......... 196 16.6.2.multiplexed mode .... ...................................................................... ......... 199 17. port input/output............ ............................................................................. ......... 203 17.1.ports 0 through 3 and the priority crossbar decoder.... ............... .................. 204 17.1.1.crossbar pin assignment and allocation .......... ............................ ......... 205 17.1.2.configuring the output mo des of the port pins........ ............ .................. 206 17.1.3.configuring port pins as digital inputs....... ................................. ........... 206 17.1.4.weak pullups .......... ...................................................................... ......... 207 17.1.5.configuring port 1, 2, and 3 pins as anal og inputs ............. .................. 207 17.1.6.external memory interface pin assignments ............. ................. ........... 208 17.1.7.crossbar pin assignment example.............. ................................. ......... 210 17.2.ports 4 through 7 ........ ........................................................................... ......... 220 17.2.1.configuring ports whic h are not pinned out............. ................. ........... 221 17.2.2.configuring the output mo des of the port pins........ ............ .................. 221 17.2.3.configuring port pins as digital inputs....... ................................. ........... 221 17.2.4.weak pullups .......... ...................................................................... ......... 221 17.2.5.external memory interfac e ............................................................ ......... 221 18. controller area network (can0) ... ............................................................. ......... 227 18.1.bosch can controller operation........................................................... ......... 228 18.1.1.can controller timing ....... ........................................................... ......... 229 c8051f040/1/2/3/4/5/6/7 6 rev. 1.5 18.1.2.example timing calculat ion for 1 mbit/sec communi cation ................. 229 18.2.can registers..... .................................................................................. ......... 231 18.2.1.can controller protocol r egisters............... ................................. ......... 231 18.2.2.message object interface registers ............................................. ......... 231 18.2.3.message handler registers... ................. .............. ............... .................. 232 18.2.4.cip-51 mcu special functi on registers .......... ............................ ......... 232 18.2.5.using can0adr, can0dath, an d candatl to access can registers . 232 18.2.6.can0adr autoincr ement feature ......... .............. ............... .................. 232 19. system management bus/i 2 c bus (smbus0) ........ ................................. ......... 239 19.1.supporting documents ............. ............................................................. ......... 240 19.2.smbus protocol........ ............................................................................. ......... 241 19.2.1.arbitration......... ............................................................................. ......... 241 19.2.2.clock low extension........ ............................................................. ......... 242 19.2.3.scl low timeout.... ...................................................................... ......... 242 19.2.4.scl high (smbus free) ti meout .............. ................................. ........... 242 19.3.smbus transfer modes... ...................................................................... ......... 242 19.3.1.master transmitter mode .. ............... ............................................. ......... 242 19.3.2.master receiver mode .............. .................................................. ........... 243 19.3.3.slave transmitter mode .... ............... ............................................. ......... 243 19.3.4.slave receiver mode ....... ............................................................. ......... 244 19.4.smbus special function regist ers ................................................................ 245 19.4.1.control register ... ......................................................................... ......... 245 19.4.2.clock rate register ......... ............................................................. ......... 248 19.4.3.data register ....... ......................................................................... ......... 249 19.4.4.address register..... ...................................................................... ......... 249 19.4.5.status register............ .................................................................. ......... 250 20. enhanced serial peripheral interface (spi0)..... ................................................. 255 20.1.signal descriptions....... ......................................................................... ......... 256 20.1.1.master out, slave in (mos i)...................... ................................. ........... 256 20.1.2.master in, slave out (miso)............... .......................................... ......... 256 20.1.3.serial clock (sck) ........... ............................................................. ......... 256 20.1.4.slave select (nss) .......... ............................................................. ......... 256 20.2.spi0 master mode operation . ............................................................... ......... 257 20.3.spi0 slave mode operation ..... ............................................................. ......... 259 20.4.spi0 interrupt sources ........ .................................................................. ......... 259 20.5.serial clock timing... ............................................................................. ......... 260 20.6.spi special function registers . ............... ............................................. ......... 261 21. uart0................ ........................................................................................... ......... 265 21.1.uart0 operational modes ...... ............................................................. ......... 266 21.1.1.mode 0: synchronous mode .. ................. .............. ............... .................. 266 21.1.2.mode 1: 8-bit uart, variable baud rate.. ................................. ........... 267 21.1.3.mode 2: 9-bit uart, fix ed baud rate .......... ............................... ......... 269 21.1.4.mode 3: 9-bit uart, variable baud rate.. ................................. ........... 270 21.2.multiprocessor communications ... ........................................................ ......... 270 c8051f040/1/2/3/4/5/6/7 rev. 1.5 7 21.3.configuration of a masked a ddress ................... ................................. ........... 271 21.4.broadcast addressing .. ......................................................................... ......... 271 21.5.frame and transmission error detection........ .............. ............... .................. 272 22. uart1................ ........................................................................................... ......... 277 22.1.enhanced baud rate g eneration.................. ................................................. 278 22.2.operational modes ....... ......................................................................... ......... 279 22.2.1.8-bit uart ........... ......................................................................... ......... 279 22.2.2.9-bit uart ........... ......................................................................... ......... 280 22.3.multiprocessor communications ... ........................................................ ......... 281 23. timers................ ............................................................ ............... .............. ........... 28 7 23.1.timer 0 and ti mer 1 ............... ............................................................... ......... 287 23.1.1.mode 0: 13-bit counter/timer ................. .............. ............... .................. 287 23.1.2.mode 1: 16-bit counter/timer ................. .............. ............... .................. 288 23.1.3.mode 2: 8-bit counter/tim er with auto-reload.......... ................. ........... 289 23.1.4.mode 3: two 8-bit counter /timers (timer 0 only)..... ................. ........... 290 23.2.timer 2, timer 3, and timer 4 . ............... ............................................... ......... 295 23.2.1.configuring timer 2, 3, and 4 to count down............ ................. ........... 295 23.2.2.capture mode ......... ...................................................................... ......... 296 23.2.3.auto-reload mode .... .................................................................. ........... 297 23.2.4.toggle output mode ........ ............................................................. ......... 298 24. programmable counter array ....... ............................................................. ......... 303 24.1.pca counter/timer ............. .................................................................. ......... 304 24.2.capture/compare modules ...... ............................................................. ......... 305 24.2.1.edge-triggered captur e mode................. .............. ............... .................. 306 24.2.2.software timer (compare) mode................. ................................. ......... 307 24.2.3.high-speed output mode ..... ........................................................ ......... 308 24.2.4.frequency output mode ....... ........................................................ ......... 309 24.2.5.8-bit pulse width modulato r mode............... ................................. ......... 310 24.2.6.16-bit pulse width modulat or mode............. ................................. ......... 311 24.3.register descriptions for pca0 ............................................................. ......... 312 25. jtag (ieee 1149.1) ........ ............................................................................. ......... 317 25.1.boundary scan ............. ......................................................................... ......... 318 25.1.1.extest instruction.......... ............................................................. ......... 319 25.1.2.sample instruction ......... ............................................................. ......... 319 25.1.3.bypass instruction ......... ............................................................. ......... 319 25.1.4.idcode instruction.......... ............................................................. ......... 319 25.2.flash programming commands.... ........................................................ ......... 321 25.3.debug support ........... ........................................................................... ......... 324 document change list............... ...................................................................... ........ 325 contact information.......... ................................................................................ ........ 326 c8051f040/1/2/3/4/5/6/7 8 rev. 1.5 n otes : c8051f040/1/2/3/4/5/6/7 rev. 1.5 9 list of figures 1. system overview figure 1.1. c8051f040/2 block di agram ........................................................ ......... 21 figure 1.2. c8051f041/3 block di agram ........................................................ ......... 22 figure 1.3. c8051f044/6 block di agram ........................................................ ......... 23 figure 1.4. c8051f045/7 block di agram ........................................................ ......... 24 figure 1.5. comparison of pe ak mcu execution speeds ......... ................. ............. 25 figure 1.6. on-board cl ock and reset ............... .......................................... ........... 26 figure 1.7. on-chip memory map. ................... ............................................. ........... 27 figure 1.8. development/in-syst em debug diagram................. ................. ............. 28 figure 1.9. digital cro ssbar diagram ............... ............................................. ........... 29 figure 1.10. pca block diagram.... ............................................................... ........... 30 figure 1.11. can controll er diagram........... ................................................. ........... 31 figure 1.12. 10/12-bit ad c block diagram ........... .......................................... ......... 32 figure 1.13. 8-bit adc diagram..... ............................................................... ........... 33 figure 1.14. compar ator and dac diagram ....... .......................................... ........... 34 2. absolute maximum ratings 3. global dc electri cal characteristic 4. pinout and package definitions figure 4.1. tqfp-100 pinout diagr am............. ............................................. ........... 43 figure 4.2. tqfp-100 package draw ing ........................................................ ......... 44 figure 4.3. tqfp-64 pinou t diagram.................. .......................................... ........... 45 figure 4.4. tqfp-64 package draw ing ........................................................ ........... 46 5. 12-bit adc (adc0, c8051f040/1 only) figure 5.1. 12-bit adc0 functi onal block diagram ..... ................................. ........... 47 figure 5.2. analog input diagram .. ............................................................... ........... 48 figure 5.3. high voltage difference amplifie r functional diagram ... .............. ......... 52 figure 5.4. 12-bit adc track and conversion example timing ................. ............. 55 figure 5.5. adc0 equiva lent input circuits. ............... ................................. ............. 56 figure 5.6. temperature sensor transfer function ..... ................................. ........... 57 figure 5.7. adc0 data word ex ample ......................................................... ........... 61 figure 5.8. 12-bit adc0 wi ndow interrupt example: ? right justified single-ended data ................. ............................ ........... 63 figure 5.9. 12-bit adc0 wi ndow interrupt example: ? right justified differential da ta.................................................. ........... 64 figure 5.10. 12-bit adc0 window interrupt example: ? left justified single-ended da ta.................... ............................ ........... 65 figure 5.11. 12-bit ad c0 window interrupt example: lef t justified differential data . 66 6. 10-bit adc (adc 0, c8051f042/3/4/5/6/7 only) figure 6.1. 10-bit adc0 functi onal block diagram ..... ................................. ........... 69 figure 6.2. analog input diagram .. ............................................................... ........... 70 figure 6.3. high voltage difference amplifie r functional diagram ... .............. ......... 74 figure 6.4. 10-bit adc track and conversion example timing ................. ............. 77 c8051f040/1/2/3/4/5/6/7 10 rev. 1.5 figure 6.5. adc0 equiva lent input circuits. ............... ................................. ............. 78 figure 6.6. temperature sensor transfer function ..... ................................. ........... 79 figure 6.7. adc0 data word ex ample ......................................................... ........... 83 figure 6.8. 10-bit adc0 wi ndow interrupt example: ? right justified single-ended data ................. ............................ ........... 85 figure 6.9. 10-bit adc0 wi ndow interrupt example: ? right justified differential da ta.................................................. ........... 86 figure 6.10. 10-bit adc0 window interrupt example: ? left justified single-ended da ta.................... ............................ ........... 87 figure 6.11. 10-bit ad c0 window interrupt example: lef t justified differential data . 88 7. 8-bit adc (adc2, c8051f040/1/2/3 only) figure 7.1. adc2 functional bl ock diagram.............. ................................. ............. 91 figure 7.2. adc2 track and c onversion example ti ming............ ................ ........... 93 figure 7.3. adc2 equiva lent input circuit........ ............................................. ........... 94 figure 7.4. adc2 data word ex ample ......................................................... ........... 99 figure 7.5. adc window co mpare examples, si ngle-ended mode...... ................ 101 figure 7.6. adc window com pare examples, differ ential mode .......... ................ 102 8. dacs, 12-bit voltage m ode (c8051f040/1/2/3 only) figure 8.1. dac functi onal block diagram......... .......................................... ......... 105 9. voltage reference (c8051f040/2/4/6) figure 9.1. voltage reference functional block diagram ....... ............ .................. 113 10. voltage reference (c8051f041/3/5/7) figure 10.1. voltage reference functional block diagram...... ............ .................. 117 11. comparators figure 11.1. compar ator functional block diagram ......... ............................ ......... 121 figure 11.2. compar ator hysteresis pl ot ................ .............. ............... .................. 122 12. cip-51 microcontroller figure 12.1. cip-51 block diagram.............. ................................................. ......... 127 figure 12.2. memory map ........... .................................................................. ......... 133 figure 12.3. sfr page stack................ ........................................................ ......... 136 figure 12.4. sfr p age stack while using sfr page 0x 0f to access port 5...... 137 figure 12.5. sfr p age stack after adc2 window comparator in terrupt occurs . 138 figure 12.6. sfr page stack upon pca interr upt occurring during an adc2 isr.... 139 figure 12.7. sfr page stack upon return from pca inte rrupt ............. .............. 140 figure 12.8. sfr p age stack upon return from adc2 window interrupt ........... 141 13. reset sources figure 13.1. rese t sources.............. ............................................................. ......... 165 figure 13.2. reset timing ........... .................................................................. ......... 166 14. oscillators figure 14.1. oscillator diagram............... ............................................................... 173 figure 14.2. 32.768 khz external crystal example...... ................................. ......... 177 15. flash memory figure 15.1. flash program me mory map and security bytes. ............ .................. 181 c8051f040/1/2/3/4/5/6/7 rev. 1.5 11 16. external data memory interface and on-chip xram figure 16.1. multiplex ed configuration example. .......................................... ......... 191 figure 16.2. non-multip lexed configuration example ......... ................................... 192 figure 16.3. emif operating modes .............. ............................................... ......... 193 figure 16.4. non-multip lexed 16-bit movx timing ................................................ 196 figure 16.5. non-multiplexed 8-bit movx without bank sele ct timing ................. 197 figure 16.6. non-multip lexed 8-bit movx with bank sele ct timing ........ .............. 198 figure 16.7. multiplexed 16-bit movx timing............ ................................. ........... 199 figure 16.8. multiplexed 8-bit movx without bank select ti ming .............. ........... 200 figure 16.9. multiplexed 8-bit movx with bank select timing ............ .................. 201 17. port input/output figure 17.1. port i/o ce ll block diagram ............ .......................................... ......... 203 figure 17.2. port i/o functional block diagram ................ ............................ ......... 204 figure 17.3. priority crossbar decode table .......... .............. ............... .................. 205 figure 17.4. priority crossbar decode table .......... .............. ............... .................. 208 figure 17.5. priority crossbar decode table .......... .............. ............... .................. 209 figure 17.6. crossbar example:.. .................................................................. ......... 211 18. controller area network (can0) figure 18.1. typical can bus configuration....... .......................................... ......... 227 figure 18.2. can controll er diagram........... ................................................. ......... 228 figure 18.3. four segm ents of a can bit time .. .......................................... ......... 229 figure 18.4. can0dath: can data access regi ster high byte ........ .................. 234 19. system management bus/i 2 c bus (smbus0) figure 19.1. smbus0 blo ck diagram ........... ................................................. ......... 239 figure 19.2. typical smbu s configuration .......... .......................................... ......... 240 figure 19.3. smbus transac tion ............. ............................................................... 241 figure 19.4. typical ma ster transmitter sequence............. ................................... 242 figure 19.5. typical ma ster receiver sequence................. ................................... 243 figure 19.6. typical slave trans mitter sequence........ ................................. ......... 243 figure 19.7. typical slave rece iver sequence............ ................................. ......... 244 20. enhanced serial peripheral interface (spi0) figure 20.1. spi bl ock diagram ............ ........................................................ ......... 255 figure 20.2. multiple -master mode connection diagram ...... ............... .................. 258 figure 20.3. 3-wire single master and sl ave mode connection di agram ............. 258 figure 20.4. 4-wire single master and sl ave mode connection di agram ............. 258 figure 20.5. data/clock timing diagram .............. ................................................. 260 21. uart0 figure 21.1. uart0 block diagram ............. ................................................. ......... 265 figure 21.2. uart 0 mode 0 timing diagram ..... .......................................... ......... 266 figure 21.3. uart0 mode 0 interconnect........... .......................................... ......... 267 figure 21.4. uart 0 mode 1 timing diagram ..... .......................................... ......... 267 figure 21.5. uart0 mo des 2 and 3 timing diagram ........... ............... .................. 269 figure 21.6. uart0 mo des 1, 2, and 3 interconnect diagram ............ .................. 269 figure 21.7. uart multi-proc essor mode interconne ct diagram .......... ................ 272 c8051f040/1/2/3/4/5/6/7 12 rev. 1.5 22. uart1 figure 22.1. uart1 block diagram ............. ................................................. ......... 277 figure 22.2. uart1 baud rate logic ............ ............................................... ......... 278 figure 22.3. uart interconnect di agram ............. ................................................. 279 figure 22.4. 8-bit uart timing diagram............ .......................................... ......... 279 figure 22.5. 9-bit uart timing diagram............ .......................................... ......... 280 figure 22.6. uart multi-proc essor mode interconne ct diagram .......... ................ 281 23. timers figure 23.1. t0 mode 0 bl ock diagram............... .......................................... ......... 288 figure 23.2. t0 mode 2 bl ock diagram............... .......................................... ......... 289 figure 23.3. t0 mode 3 bl ock diagram............... .......................................... ......... 290 figure 23.4. tn capture mode bl ock diagram ............. ................................. ......... 296 figure 23.5. tn auto-reload mode and toggle mode block dia gram ........... ......... 297 24. programmable counter array figure 24.1. pca block diagram.... ............................................................... ......... 303 figure 24.2. pca counter /timer block diagram.... ................................................ 304 figure 24.3. pca interrupt blo ck diagram ................. ................................. ........... 305 figure 24.4. pca captur e mode diagram............. ................................................. 306 figure 24.5. pca software time r mode diagram ........ ................................. ......... 307 figure 24.6. pca high- speed output mode diagram........... ............... .................. 308 figure 24.7. pca fr equency output mode ......... .......................................... ......... 309 figure 24.8. pca 8-bit pwm mode diagram .......... .............. ............... .................. 310 figure 24.9. pca 16-bit pwm mode ............................................................. ......... 311 25. jtag (ieee 1149.1) c8051f040/1/2/3/4/5/6/7 rev. 1.5 13 list of tables 1. system overview table 1.1. product select ion guide ................. ............................................. ........... 20 2. absolute maximum ratings table 2.1. absolute maximum rati ngs* ............. .......................................... ........... 35 3. global dc electri cal characteristic table 3.1. global dc electrical characteristics ........... ................................. ........... 36 4. pinout and package definitions table 4.1. pin definitions ................. ............................................................. ........... 37 5. 12-bit adc (adc0, c8051f040/1 only) table 5.1. amux selection chart (amx 0ad3?0 and amx0cf3?0 bits) ................ 50 table 5.2. 12-bit adc0 electrical characteristics ....... ................................. ........... 67 table 5.3. high-voltage differ ence amplifier electr ical characteristi cs ......... ......... 68 6. 10-bit adc (adc 0, c8051f042/3/4/5/6/7 only) table 6.1. amux selection chart (amx0ad3 -0 and amx0cf3-0 bits ) ......... ......... 72 table 6.2. 10-bit adc0 electrical characteristics ....... ................................. ........... 89 table 6.3. high-voltage differ ence amplifier electr ical characteristi cs ......... ......... 90 7. 8-bit adc (adc2, c8051f040/1/2/3 only) table 7.1. amux selection chart (amx2ad2 -0 and amx2cf3-0 bits ) ......... ......... 96 table 7.2. adc2 elec trical characteristics .... ............................................... ......... 103 8. dacs, 12-bit voltage m ode (c8051f040/1/2/3 only) table 8.1. dac electrical characteristics ........ ............................................. ......... 111 9. voltage reference (c8051f040/2/4/6) table 9.1. voltage reference elec trical characteristi cs .............. ................ ......... 115 10. voltage reference (c8051f041/3/5/7) table 10.1. voltage reference electrical charac teristics ....... ............ .................. 119 11. comparators table 11.1. comparator electrical characteristics .... ................................. ........... 126 12. cip-51 microcontroller table 12.1. cip-51 instruction set summary ............ ................................. ........... 129 table 12.2. special func tion register (sf r) memory map . ............... .................. 144 table 12.3. special functi on registers .............. .......................................... ......... 146 table 12.4. interrupt summ ary ................. .................................................. ........... 154 13. reset sources table 13.1. reset electrical char acteristics ........... .............. ............... .................. 171 14. oscillators table 14.1. internal oscillator el ectrical characteristics ...... ............... .................. 175 15. flash memory table 15.1. flash electric al characteristics ....... .......................................... ......... 180 16. external data memory interface and on-chip xram table 16.1. ac parameters for external memory interface ..... ............ .................. 202 17. port input/output table 17.1. port i/o dc electrical characteristics ............ ............................ ......... 203 c8051f040/1/2/3/4/5/6/7 14 rev. 1.5 18. controller area network (can0) table 18.1. background system info rmation ......... .............. ............... .................. 229 table 18.2. can register index and reset values ........... ................................... 233 19. system management bus/i 2 c bus (smbus0) table 19.1. smb0sta status codes and states ........ ................................. ......... 252 20. enhanced serial peripheral interface (spi0) 21. uart0 table 21.1. uart0 modes ............ ............................................................... ......... 266 table 21.2. oscillator frequencie s for standard baud rates ... ................. ........... 273 22. uart1 table 22.1. timer settings for standard baud rates using the internal 24.5 mhz os- cillator ........... ............................................................................. ......... 284 table 22.2. timer settings for standard baud rates using an external 25.0 mhz os- cillator ........... ............................................................................. ......... 284 table 22.3. timer settings for standard baud rates using an external 22.1184 mhz oscillator ........... ......................................................................... ......... 285 table 22.4. timer settings for standard baud rates usin g an external 18.432 mhz oscillator ........... ......................................................................... ......... 285 table 22.5. timer settings for standard baud rates using an external 11.0592 mhz oscillator ........... ......................................................................... ......... 286 table 22.6. timer settings for standard baud rates usin g an external 3.6864 mhz oscillator ........... ......................................................................... ......... 286 23. timers 24. programmable counter array table 24.1. pca timebase input op tions ............ ................................................. 304 table 24.2. pca0cpm register settings for pca captur e/compare modules .... 305 25. jtag (ieee 1149.1) table 25.1. boundary data register bit definitions ......... ............................ ......... 318 c8051f040/1/2/3/4/5/6/7 rev. 1.5 15 list of registers sfr definition 5.1. amx0cf: amux0 configuration . . . . . . . . . . . . . . . . . . . . . . . . . . 49 sfr definition 5.2. amx0sl: amux0 channel select . . . . . . . . . . . . . . . . . . . . . . . . . 49 sfr definition 5.3. amx0prt: port 3 pin selection . . . . . . . . . . . . . . . . . . . . . . . . . . 51 sfr definition 5.4. hva0 cn: high voltage difference amplifier control . . . . . . . . . . . 53 sfr definition 5.5. adc0cf: adc0 configuration register . . . . . . . . . . . . . . . . . . . . 58 sfr definition 5.6. adc0cn: adc0 control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 sfr definition 5.7. adc0h: adc0 data word msb . . . . . . . . . . . . . . . . . . . . . . . . . . 60 sfr definition 5.8. adc0l: adc0 data word lsb . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 sfr definition 5.9. adc0gth: a dc0 greater-than data high byte . . . . . . . . . . . . . 62 sfr definition 5.10. adc0 gtl: adc0 greater-than data low byte . . . . . . . . . . . . . 62 sfr definition 5.11. adc0lth: ad c0 less-than data high byte . . . . . . . . . . . . . . . 62 sfr definition 5.12. adc0ltl: ad c0 less-than data low byte . . . . . . . . . . . . . . . . 63 sfr definition 6.1. amx0cf: amux0 configuration . . . . . . . . . . . . . . . . . . . . . . . . . . 71 sfr definition 6.2. amx0sl: amux0 channel select . . . . . . . . . . . . . . . . . . . . . . . . 71 sfr definition 6.3. amx0prt: port 3 pin selection . . . . . . . . . . . . . . . . . . . . . . . . . . 73 sfr definition 6.4. hva0 cn: high voltage difference amplifier control . . . . . . . . . . . 75 sfr definition 6.5. adc0cf: adc0 c onfiguration . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 sfr definition 6.6. adc0cn: adc0 control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 sfr definition 6.7. adc0h: adc0 data word msb . . . . . . . . . . . . . . . . . . . . . . . . . . 82 sfr definition 6.8. adc0l: adc0 data word lsb . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 sfr definition 6.9. adc0gth: a dc0 greater-than data high byte . . . . . . . . . . . . . 84 sfr definition 6.10. adc0 gtl: adc0 greater-than data low byte . . . . . . . . . . . . . 84 sfr definition 6.11. adc0lth: ad c0 less-than data high byte . . . . . . . . . . . . . . . 84 sfr definition 6.12. adc0ltl: ad c0 less-than data low byte . . . . . . . . . . . . . . . . 85 sfr definition 7.1. amx2cf: amux2 configuration . . . . . . . . . . . . . . . . . . . . . . . . . . 95 sfr definition 7.2. amx2sl: amux2 channel select . . . . . . . . . . . . . . . . . . . . . . . . . 95 sfr definition 7.3. adc2cf: adc2 c onfiguration . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 sfr definition 7.4. adc2cn: adc2 control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 sfr definition 7.5. adc2: a dc2 data w ord . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 sfr definition 7.6. adc2 gt: adc2 greater-than data . . . . . . . . . . . . . . . . . . . . . . 100 sfr definition 7.7. adc2lt : adc2 less-than data . . . . . . . . . . . . . . . . . . . . . . . . . 100 sfr definition 8.1. dac0h: dac0 hi gh byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 sfr definition 8.2. dac0l: dac0 low byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 sfr definition 8.3. dac0cn: dac0 c ontrol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 sfr definition 8.4. dac1h: dac1 hi gh byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 sfr definition 8.5. dac1l: dac1 low byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 sfr definition 8.6. dac1cn: dac1 c ontrol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 sfr definition 9.1. ref0cn : reference control . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 sfr definition 10.1. ref0cn: refer ence control . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 sfr definition 11.1. cptncn : comparator 0, 1, and 2 control . . . . . . . . . . . . . . . . . 124 sfr definition 11.2. cptnmd: com parator mode selection . . . . . . . . . . . . . . . . . . . 125 sfr definition 12.1. sfr page control register: sf rpgcn . . . . . . . . . . . . . . . . . . 142 sfr definition 12.2. sfr p age register: sfrpage . . . . . . . . . . . . . . . . . . . . . . . . . 142 c8051f040/1/2/3/4/5/6/7 16 rev. 1.5 sfr definition 12.3. sfr next regi ster: sfrnext . . . . . . . . . . . . . . . . . . . . . . . . . 143 sfr definition 12.4. sfr last regi ster: sfrlast . . . . . . . . . . . . . . . . . . . . . . . . . . 143 sfr definition 12.5. sp: sta ck pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 sfr definition 12.6. dpl: data poin ter low byte . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 sfr definition 12.7. dph: da ta pointer high byte . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 sfr definition 12.8. psw: program st atus word . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 sfr definition 12.9. acc: ac cumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 sfr definition 12.10. b: b regi ster . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 sfr definition 12.11. ie: inte rrupt enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 sfr definition 12.12. ip: interrupt prio rity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 sfr definition 12.13. eie1: extended interrupt enable 1 . . . . . . . . . . . . . . . . . . . . . 159 sfr definition 12.14. eie2: extended interrupt enable 2 . . . . . . . . . . . . . . . . . . . . . 160 sfr definition 12.15. eip1: extended interrupt priority 1 . . . . . . . . . . . . . . . . . . . . . 161 sfr definition 12.16. eip2: extended interrupt priority 2 . . . . . . . . . . . . . . . . . . . . . 162 sfr definition 12.18. pc on: power control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 sfr definition 13.1. wdtcn: watch dog timer control . . . . . . . . . . . . . . . . . . . . . . 169 sfr definition 13.2. rstsrc: reset source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 sfr definition 14.1. oscicl: intern al oscillator calibration . . . . . . . . . . . . . . . . . . . 174 sfr definition 14.2. oscicn: inter nal oscillator control . . . . . . . . . . . . . . . . . . . . . 174 sfr definition 14.3. clksel: oscillator clock selecti on . . . . . . . . . . . . . . . . . . . . . 175 sfr definition 14.4. oscxcn: external oscillator c ontrol . . . . . . . . . . . . . . . . . . . . 176 sfr definition 15.1. flacl: flash access limit . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 sfr definition 15.2. flscl: flash memory control . . . . . . . . . . . . . . . . . . . . . . . . . 184 sfr definition 15.3. psctl: prog ram store read/write control . . . . . . . . . . . . . . . 185 sfr definition 16.1. emi0 cn: external memory interface cont rol . . . . . . . . . . . . . . 189 sfr definition 16.2. emi0cf: exter nal memory configuration . . . . . . . . . . . . . . . . . 190 sfr definition 16.3. emi0 tc: external memory timing control . . . . . . . . . . . . . . . . 195 sfr definition 17.1. xbr0: port i/o crossbar regist er 0 . . . . . . . . . . . . . . . . . . . . . 212 sfr definition 17.2. xbr1: port i/o crossbar regist er 1 . . . . . . . . . . . . . . . . . . . . . 213 sfr definition 17.3. xbr2: port i/o crossbar regist er 2 . . . . . . . . . . . . . . . . . . . . . 214 sfr definition 17.4. xbr3: port i/o crossbar regist er 3 . . . . . . . . . . . . . . . . . . . . . 215 sfr definition 17.5. p0: port0 data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215 sfr definition 17.6. p0mdout: port 0 output mode . . . . . . . . . . . . . . . . . . . . . . . . . 216 sfr definition 17.7. p1: port1 data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216 sfr definition 17.8. p1mdin : port1 input mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217 sfr definition 17.9. p1mdout: port 1 output mode . . . . . . . . . . . . . . . . . . . . . . . . . 217 sfr definition 17.10. p2: port 2 data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218 sfr definition 17.11. p2mdin : port2 input mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 218 sfr definition 17.12. p2mdout: port 2 output mode . . . . . . . . . . . . . . . . . . . . . . . . 219 sfr definition 17.13. p3: port 3 data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219 sfr definition 17.14. p3mdin : port3 input mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 220 sfr definition 17.15. p3mdout: port 3 output mode . . . . . . . . . . . . . . . . . . . . . . . . 220 sfr definition 17.16. p4: port 4 data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222 sfr definition 17.17. p4mdout: port 4 output mode . . . . . . . . . . . . . . . . . . . . . . . . 222 sfr definition 17.18. p5: port 5 data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223 c8051f040/1/2/3/4/5/6/7 rev. 1.5 17 sfr definition 17.19. p5mdout: port 5 output mode . . . . . . . . . . . . . . . . . . . . . . . . 223 sfr definition 17.20. p6: port 6 data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224 sfr definition 17.21. p6mdout: port 6 output mode . . . . . . . . . . . . . . . . . . . . . . . . 224 sfr definition 17.22. p7: port 7 data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225 sfr definition 17.23. p7mdout: port 7 output mode . . . . . . . . . . . . . . . . . . . . . . . . 225 sfr definition 18.1. can0datl: can data access register low byte . . . . . . . . . . 235 sfr definition 18.2. can0adr: can address index . . . . . . . . . . . . . . . . . . . . . . . . 235 sfr definition 18.3. can0cn: can control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236 sfr definition 18.4. can0tst: can test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236 sfr definition 18.5. can0sta: can status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237 sfr definition 19.1. smb0cn : smbus0 control . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247 sfr definition 19.2. smb0cr : smbus0 clock rate . . . . . . . . . . . . . . . . . . . . . . . . . 248 sfr definition 19.3. smb0dat: smbus0 data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249 sfr definition 19.4. smb0a dr: smbus0 address . . . . . . . . . . . . . . . . . . . . . . . . . . 250 sfr definition 19.5. smb0sta: smbus0 status . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251 sfr definition 20.1. spi0cfg: spi0 configuration . . . . . . . . . . . . . . . . . . . . . . . . . . 261 sfr definition 20.2. spi0cn: spi0 control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262 sfr definition 20.3. spi0ck r: spi0 clock rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263 sfr definition 20.4. spi0dat: spi0 data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264 sfr definition 21.1. scon0: uart0 control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274 sfr definition 21.2. ssta 0: uart0 status and clock selection . . . . . . . . . . . . . . . 275 sfr definition 21.3. sbuf0: uart0 data buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . 276 sfr definition 21.4. saddr0: uart0 slave address . . . . . . . . . . . . . . . . . . . . . . . 276 sfr definition 21.5. sade n0: uart0 slave address enable . . . . . . . . . . . . . . . . . 276 sfr definition 22.1. scon1: serial port 1 control . . . . . . . . . . . . . . . . . . . . . . . . . . 282 sfr definition 22.2. sbuf1: serial (uart1) port data buffer . . . . . . . . . . . . . . . . . 283 sfr definition 23.1. tcon: timer cont rol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291 sfr definition 23.2. tmod: ti mer mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292 sfr definition 23.3. ckcon: cl ock control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293 sfr definition 23.4. tl0: timer 0 low byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293 sfr definition 23.5. tl1: timer 1 low byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 294 sfr definition 23.6. th0: timer 0 hi gh byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 294 sfr definition 23.7. th1: timer 1 hi gh byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 294 sfr definition 23.8. tmrncn: timer n control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299 sfr definition 23.9. tmrncf: timer n configuration . . . . . . . . . . . . . . . . . . . . . . . . 300 sfr definition 23.10. rcapnl: time r n capture register low byte . . . . . . . . . . . . . 301 sfr definition 23.11. rcapnh: ti mer n capture register high by te . . . . . . . . . . . . 301 sfr definition 23.12. tmrnl: timer n low byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301 sfr definition 23.13. tmrnh timer n high byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . 302 sfr definition 24.1. pca0cn: pca control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 312 sfr definition 24.2. pca0md: pca0 mo de . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 313 sfr definition 24.3. pc a0cpmn: pca0 capture/ compare mode . . . . . . . . . . . . . . 314 sfr definition 24.4. pca0l: pca0 counter/timer low byte . . . . . . . . . . . . . . . . . . 315 sfr definition 24.5. pca0h: pca0 counter/timer high byte . . . . . . . . . . . . . . . . . . 315 sfr definition 24.6. pca0cpln: pc a0 capture module low byte . . . . . . . . . . . . . . 316 c8051f040/1/2/3/4/5/6/7 18 rev. 1.5 sfr definition 24.7. pca0cphn: pca0 capture module high byte . . . . . . . . . . . . . 316 jtag register definition 25.1. ir: jtag instructio n register . . . . . . . . . . . . . . . . . . 317 jtag register definiti on 25.2. deviceid: jtag device id register . . . . . . . . . . . . 320 jtag register definiti on 25.3. flashcon: jtag flash control regist er . . . . . . . . 322 jtag register definition 25.4. flashdat: jtag flash data . . . . . . . . . . . . . . . . . 323 jtag register definiti on 25.5. flashadr: jtag flash addres s . . . . . . . . . . . . . . 323 c8051f040/1/2/3/4/5/6/7 rev. 1.5 19 1. system overview the c8051f04x family of devices are fully integrated mixed-signal system-on-a-chip mcus with 64 digital i/o pins (c8051f040/2/4/6) or 32 digital i/o pins (c8051f041/3/5/7), and an integrated can 2.0b control- ler. highlighted features are listed below; refer to table 1.1 for specific product feature selection. ? high-speed pipelined 8051-compatible cip-51 microcontroller core (up to 25 mips) ? controller area network (can 2.0b ) controller with 32 message object s, each with its own indentifier mask. ? in-system, full-speed, non-intrusive debug interface (on-chip) ? true 12-bit (c8051f040/1) or 10-bit (c8051f042/3/4/5/6/7) 100 ksps 8-channel adc with pga and analog multiplexer ? high voltage difference amplifier input to the 12/10-bit adc (60 v peak-to-peak) with programmable ga in. ? true 8-bit 500 ksps 8-channel adc with pga and anal og multiplexer (c8051f040/1/2/3) ? two 12-bit dacs with programmable update scheduling (c8051f040/1/2/3) ?64 kb (c8051f040/1 /2/3/4/5) or 32 kb (c8051f046/7) of in-system programmable flash memory ? 4352 (4096 + 256) bytes of on-chip ram ? external data memory interface with 64 kb address space ? spi, smbus/i 2 c, and (2) uart serial interfaces implemented in hardware ? five general purpose 16-bit timers ? programmable counter/timer array with six capture/compare modules ? on-chip watchdog timer, v dd monitor, and temperature sensor with on-chip v dd monitor, watchdog timer, an d clock oscillator, the c8051f04 x family of devices are truly stand-alone system-on-a-chip solutions. all analog and digital peripherals are enabled/disabled and con- figured by user firmware. the flash memory can be reprogrammed even in-circuit, providing non-volatile data storage, and also allowing field upgrades of the 8051 firmware. on-board jtag debug circuitry allows non-intrusive (u ses no on-chip resources), full speed, in-circuit pro- gramming and debugging us ing the production mcu inst alled in the final applic ation. this debug system supports inspection and modification of memory and registers, setting breakpoi nts, watchpoints, single stepping, run, and halt commands. all analog and di gital peripherals are fully functional while debugging using jtag. each mcu is specified for 2.7 v to 3.6 v operation over the industrial temperature range (?45 to +85 c). the port i/os, /rst, and jtag pins are tolerant for input signals up to 5 v. the c8051f040/2/4/6 are avail- able in a 100-pin tqfp and the c8051f041/3/5/7 are available in a 64-pin tqfp. c8051f040/1/2/3/4/5/6/7 20 rev. 1.5 table 1.1. product selection guide ordering part number mips (peak) flash memory ram external memory interface smbus/i 2 c and spi can uarts timers (16-bit) programmable counter array digital port i/o?s 12-bit 100ksps adc 10-bit 100ksps adc 8-bit 500 ksps adc inputs high voltage diff amp voltage reference temperature sensor dac resolution (bits) dac outputs analog comparators lead-free (rohs compliant) package c8051f040 25 64 kb 4352 ? ? ? 2 5 ? 64 ? - 8 ? ? ? 12 2 3 - 100tqfp c8051f040-gq 25 64 kb 4352 ? ? ? 2 5 ? 64 ? - 8 ? ? ? 12 2 3 ? 100tqfp c8051f041 25 64 kb 4352 ? ? ? 2 5 ? 32 ? - 8 ? ? ? 12 2 3 - 64tqfp c8051f041-gq 25 64 kb 4352 ? ? ? 2 5 ? 32 ? - 8 ? ? ? 12 2 3 ? 64tqfp c8051f042 25 64 kb 4352 ? ? ? 2 5 ? 64 - ? 8 ? ? ? 12 2 3 - 100tqfp c8051f042-gq 25 64 kb 4352 ? ? ? 2 5 ? 64 - ? 8 ? ? ? 12 2 3 ? 100tqfp c8051f043 25 64 kb 4352 ? ? ? 2 5 ? 32 - ? 8 ? ? ? 12 2 3 - 64tqfp C8051F043-GQ 25 64 kb 4352 ? ? ? 2 5 ? 32 - ? 8 ? ? ? 12 2 3 ? 64tqfp c8051f044 25 64 kb 4352 ? ? ? 2 5 ? 64 - ? ? ? ? 3 - 100tqfp c8051f044-gq 25 64 kb 4352 ? ? ? 2 5 ? 64 - ? ? ? ? 3 ? 100tqfp c8051f045 25 64 kb 4352 ? ? ? 2 5 ? 32 - ? ? ? ? 3 - 64tqfp c8051f045-gq 25 64 kb 4352 ? ? ? 2 5 ? 32 - ? ? ? ? 3 ? 64tqfp c8051f046 25 32 kb 4352 ? ? ? 2 5 ? 64 - ? ? ? ? 3 - 100tqfp c8051f046-gq 25 32 kb 4352 ? ? ? 2 5 ? 64 - ? ? ? ? 3 ? 100tqfp c8051f047 25 32 kb 4352 ? ? ? 2 5 ? 32 - ? ? ? ? 3 - 64tqfp c8051f047-gq 25 32 kb 4352 ? ? ? 2 5 ? 32 - ? ? ? ? 3 ? 64tqfp c8051f040/1/2/3/4/5/6/7 rev. 1.5 21 figure 1.1. c8051f040/2 block diagram uart1 smbus spi bus pca timers 0,1,2,3,4 vdd vdd vdd dgnd dgnd dgnd /rst xtal1 xtal2 p2.0 p2.7 p0.0 p0.7 dac1 dac1 (12-bit) vref dac0 (12-bit) ain0.0 dac0 vref uart0 8:1 monen wdt vrefd vref0 p7 latch p5 latch p6 latch p5.0/a8 p5.7/a51 p5 drv p6.0/a0 p6.7/a7 p6 drv p4 drv p4.5/ale p4.6/rd p4.7/wr p4.4 addr [7:0] addr [15:8] ctrl latch data latch a m u x 8:2 hvain+ hvain- hvref hvcap hvamp temp sensor p0 drv p1 drv p2 drv p3 drv port 0,1,2,3 &4 latches can 2.0b cantx 8 0 5 1 c o r e reset a m u x prog gain adc 100 ksps (12 or 10- bit) 32x136 canram 256 byte ram 4 kb ram p3.0 p3.7 p1.0 p1.7 64 kb flash system clock internal oscillator external oscillator circuit v dd monitor c r o s s b a r data [7:0] address [15:0] bus control digital power memories port 4 c8051f040/1/2/3/4/5/6/7 22 rev. 1.5 figure 1.2. c8051f041/3 block diagram uart1 smbus spi bus pca timers 0,1,2,3,4 vdd vdd vdd dgnd dgnd dgnd /rst xtal1 xtal2 p2.0 p2.7 p0.0 p0.7 dac1 dac1 (12-bit) vref dac0 (12-bit) ain0.0 dac0 vref uart0 8:1 monen wdt vrefa p7 latch p5 latch p6 latch p5 drv p6 drv p4 drv addr [7:0] addr [15:8] ctrl latch data latch a m u x 8:2 hvain+ hvain- hvref hvcap hvamp temp sensor p0 drv p1 drv p2 drv p3 drv port 0,1,2,3 &4 latches can 2.0b cantx 8 0 5 1 c o r e reset a m u x prog gain adc 100 ksps (12 or 10- bit) 32x136 canram 256 byte ram 4 kb ram p3.0 p3.7 p1.0 p1.7 64 kb flash system clock internal oscillator external oscillator circuit v dd monitor c r o s s b a r data [7:0] address [15:0] bus control digital power memories port 4 c8051f040/1/2/3/4/5/6/7 rev. 1.5 23 figure 1.3. c8051f044/6 block diagram uart1 smbus spi bus pca timers 0,1,2,3,4 vdd vdd vdd dgnd dgnd dgnd /rst xtal1 xtal2 p2.0 p2.7 p0.0 p0.7 vref ain0.0 vref uart0 monen wdt vref0 p7 latch p5 latch p6 latch p5.0/a8 p5.7/a51 p5 drv p6.0/a0 p6.7/a7 p6 drv p4 drv p4.5/ale p4.6/rd p4.7/wr p4.4 addr [7:0] addr [15:8] ctrl latch data latch a m u x 8:2 hvain+ hvain- hvref hvcap hvamp temp sensor p0 drv p1 drv p2 drv p3 drv port 0,1,2,3 &4 latches can 2.0b cantx 8 0 5 1 c o r e reset a m u x prog gain adc 100 ksps (10-bit) 32x136 canram 256 byte ram 4 kb ram p3.0 p3.7 p1.0 p1.7 64/32 kb flash system clock internal oscillator external oscillator circuit v dd monitor c r o s s b a r data [7:0] address [15:0] bus control digital power memories port 4 c8051f040/1/2/3/4/5/6/7 24 rev. 1.5 figure 1.4. c8051f045/7 block diagram uart1 smbus spi bus pca timers 0,1,2,3,4 vdd vdd vdd dgnd dgnd dgnd /rst xtal1 xtal2 p2.0 p2.7 p0.0 p0.7 vref ain0.0 vref uart0 monen wdt vrefa p7 latch p5 latch p6 latch p5 drv p6 drv p4 drv addr [7:0] addr [15:8] ctrl latch data latch a m u x 8:2 hvain+ hvain- hvref hvcap hvamp temp sensor p0 drv p1 drv p2 drv p3 drv port 0,1,2,3 &4 latches can 2.0b cantx 8 0 5 1 c o r e reset a m u x prog gain adc 100 ksps (10-bit) 32x136 canram 256 byte ram 4 kb ram p3.0 p3.7 p1.0 p1.7 64/32 kb flash system clock internal oscillator external oscillator circuit v dd monitor c r o s s b a r data [7:0] address [15:0] bus control digital power memories port 4 c8051f040/1/2/3/4/5/6/7 rev. 1.5 25 1.1. cip-51? microcontroller core 1.1.1. fully 8051 compatible the c8051f04x family of devices utilizes silicon labs' proprietary ci p-51 microcontroller core. the cip- 51 is fully compatible with the mc s-51? instruction set; standard 803x/805x assemblers and compilers can be used to develop software. the core has all t he peripherals included with a standard 8052, including five 16-bit counter/timers, two full- duplex uarts, 256 bytes of internal ram, 128 byte special function register (sfr) address space, and up to 8 byte-wide i/o ports. 1.1.2. improved throughput the cip-51 employs a pipelined architecture that grea tly increases its instruction throughput over the stan- dard 8051 architecture. in a standa rd 8051, all instructions except for mul and div take 12 or 24 system clock cycles to execute with a maximum system clock of 12-to-24 mhz. by contrast, the cip-51 core exe- cutes 70% of its instructions in one or two system clock cycles, with only four inst ructions taking more than four system clock cycles. the cip-51 has a total of 109 instructions. the table below shows the total number of instructions that require each execution time. with the cip-51's maximum system clock at 25 mhz, it ha s a peak throughput of 25 mips. figure 1.5 shows a comparison of peak throughputs of various 8-bit microcontrolle r cores with thei r maximum system clocks. figure 1.5. comparison of peak mcu execution speeds clocks to execute 1 2 2/3 3 3/4 4 4/5 5 8 number of instructions 26 50 5 14 7 3 1 2 1 5 10 15 20 aduc812 8051 (16 mhz clk) philips 80c51 (33 mhz clk) microchip pic17c75x (33 mhz clk) silicon labs cip-51 (25 mhz clk) mips 25 c8051f040/1/2/3/4/5/6/7 26 rev. 1.5 1.1.3. additional features the c8051f04x mcu family includes several key enhancements to the cip-51 core and peripherals to improve overall performance and ease of use in end applications. the extended interrupt handler provides 20 interrupt sources into the cip-51 (as opposed to 7 for the stan- dard 8051), allowing the numerous analog and digital peripherals to interrupt the controller. an interrupt driven system requires less interventi on by the mcu, giving it more effective throughput. the extra inter- rupt sources are very useful when building multi-tasking, real-time systems. there are up to seven reset sources for the mcu: an on-board v dd monitor, a watchdog timer, a missing clock detector, a voltage level detection from compar ator0, a forced software reset, the cnvstr0 input pin, and the /rst pin. the /rst pin is bi-directio nal, accommodating an external reset, or allowing the internally generated por to be output on the /r st pin. each reset so urce except for the v dd monitor and reset input pin may be disabled by the user in software; the v dd monitor is enabled/disabled via the monen pin. the watchdog timer may be permanently enabled in software after a power-on reset during mcu initialization. the mcu has an internal, stand alone clock generator which is used by default as the system clock after any reset. if desired, the clock sour ce may be switched on the fly to the external oscillator, which can use a crystal, ceramic resonator, capacitor, rc, or external clock source to generate the system clock. this can be extremely useful in low power applications, allowing the mcu to run from a slow (power saving) exter- nal crystal source, while periodically switching to the fast (up to 25 mhz) internal oscillator as needed. figure 1.6. on-board clock and reset wdt xtal1 xtal2 osc internal clock generator system clock cip-51 microcontroller core missing clock detector (one- shot) wdt strobe software reset extended interrupt handler clock select rst + - v dd supply reset timeout (wired-or) system reset supply monitor pre reset funnel + - cp0+ comparator0 cp0- (port i/o) crossbar cnvstr (cnvstr reset enable) (cp0 reset enable) en wdt enable en mcd enable c8051f040/1/2/3/4/5/6/7 rev. 1.5 27 1.2. on-chip memory the cip-51 has a standard 8051 program and data address configuration. it includes 256 bytes of data ram, with the upper 128 bytes dual-mapped. indirect addressing accesses the upper 128 bytes of general purpose ram, and direct addressing accesses the 128 byte sfr address space. the cip-51 sfr address space contains up to 256 sfr pages . in this way, the cip-51 mcu can accommodate the many sfrs required to control and configure the various peripherals featured on the device. the lower 128 bytes of ram are accessible via direct and indire ct addressing. the first 32 bytes are addressable as four banks of general purpose registers, and the next 16 bytes can be byte addressable or bit addressable. the cip-51 in the c8051f04x mcus additionally has an on-chip 4 kb ram block and an external memory interface (emif) for accessing off-chip data memory or memory-mapped peripherals. the on-chip 4 byte block can be addressed over the entire 64 kb exte rnal data memory address range (overlapping 4 kb boundaries). external data memory address space can be mapped to on-chip memory only, off-chip mem- ory only, or a combination of the two (addresses up to 4 kb directed to on-chip, above 4 kb directed to emif). the emif is also configurable for mult iplexed or non-multiplexed address/data lines. the mcu's program memory consists of 64 kb (c8051f040/1/2/3/4/5) or 32 kb (c8051f046/7) of flash. this memory may be reprogrammed in-system in 512 byte sectors, and requires no special off-chip pro- gramming voltage. the 512 bytes from addresses 0xfe 00 to 0xffff are reserved for the 64 kb devices. there is also a single 128 byte sector at address 0x10000 to 0x1007f, which may be useful as a small table for software constants. see figure 1.7 for the mcu system memory map. figure 1.7. on-chip memory map program/data memory (flash) (direct and indirect addressing) 0x00 0x7f upper 128 ram (indirect addressing only) 0x80 0xff special function registers (direct addressing only) data memory (ram) general purpose registers 0x1f 0x20 0x2f bit addressable lower 128 ram (direct and indirect addressing) 0x30 internal data address space external data address space xram - 4096 bytes (accessable using movx instruction) 0x0000 0x0fff off-chip xram space 0x1000 0xffff 64 kb flash (in-system programmable in 512 byte sectors) 0x0000 reserved 0xfe00 0xfdff scrachpad memory (data only) 0x1007f 0x10000 up to 256 sfr pages 1 3 0 2 f c8051f040/1/2/3/4/5 32 kb flash (in-system programmable in 512 byte sectors) 0x0000 reserved 0x8000 0x7fff scrachpad memory (data only) 0x1007f 0x10000 c8051f046/7 c8051f040/1/2/3/4/5/6/7 28 rev. 1.5 1.3. jtag debug and boundary scan the c8051f04x family has on-chip jtag bounda ry scan and debug circ uitry that provides non-intrusive, full speed, in-circuit debugging using the produc tion part installed in the end application , via the four-pin jtag interface. the jtag port is fully compliant to ieee 1149.1, providing full boundary scan for test and manufacturing purposes. silicon labs' debugging syst em supports inspection and modificati on of memory and registers, break- points, watchpoints, a stack monitor, and single step ping. no additional target ram, program memory, tim- ers, or communications channels are required. all the digital and analog peripherals are functional and work correctly while debugging. all the peripherals (except for the adc and smbus) are stalled when the mcu is halted, during single stepping, or at a breakpoi nt in order to keep them synchronized with instruc- tion execution. the c8051f040dk development kit provides all the har dware and software necessary to develop applica- tion code and perform in-circuit debugging with the c8051f04x mcus. the development kit includes two target boards and a cable to fac ilitate evaluating a simple can comm unication network. the kit also includes software with a developer's studio and de bugger, a target application board with the associated mcu installed, and the required cables and wall-mount power supply. the serial adapter takes its power from the application board; it requires roughly 20 ma at 2.7-3.6 v. for applications where there is not suffi- cient power available from the target system, the prov ided power supply can be connected directly to the serial adapter. silicon labs? debug environment is a vastly superior conf iguration for developin g and debuggi ng embed- ded applications compared to standard mcu emulators, which use on-board "ice chips" and target cables and require the mcu in the applic ation board to be socketed. silicon labs' debug environment both increases ease of use and preserves the performance of the precision, on-chip analog peripherals. figure 1.8. development/in -system debug diagram target pcb serial adapter c8051 f040 vdd gnd jtag (x4), vdd, gnd windows 95 or later integrated development environment c8051f040/1/2/3/4/5/6/7 rev. 1.5 29 1.4. programmable digital i/o and crossbar the standard 8051 ports (0, 1, 2, and 3) are available on the mcus. the c8051f040/2/4/6 have 4 addi- tional 8-bit ports (4, 5, 6, and 7) for a total of 64 general-purpose i/o ports. the ports behave like the stan- dard 8051 with a few enhancements. each port pin can be configured as either a push-pull or open-drain output. also, the "weak pullups" which are normally fixed on an 8051 can be globally disabl ed, providing additional powe r saving capabilities for low-power applications. perhaps the most unique enhancement is the digital cr ossbar. this is essentially a large digital switching network that allows mapping of internal digital syst em resources to port i/o pins on p0, p1, p2, and p3 (see figure 1.9). unlike microcontrollers with standard multiplexed digital i/o por ts, all combinations of functions are supported with all package options offered. the on-chip counter/timers, serial buses, hw interrupts, adc start of conversion input, comparator out- puts, and other digital signals in the controller can be configured to appear on the port i/o pins specified in the crossbar control registers. this allows the user to select the exact mix of general purpose port i/o and digital resources needed for the particular application. figure 1.9. digital crossbar diagram external pins digital crossbar priority decoder smbus 2 spi 4 uart0 2 pca 2 t0, t1, t2, t2ex, t3, t3ex, t4,t4ex, /int0, /int1 p1.0 p1.7 p2.0 p2.7 p0.0 p0.7 highest priority lowest priority 8 8 comptr. outputs (internal digital signals) highest priority lowest priority uart1 6 2 p3.0 p3.7 8 8 p0mdout, p1mdout, p2mdout, p3mdout registers xbr0, xbr1, xbr2, xbr3 p1mdin, p2mdin, p3mdin registers p1 i/o cells p3 i/o cells p0 i/o cells p2 i/o cells 8 port latches p0 p1 p2 8 8 8 p3 8 (p2.0-p2.7) (p1.0-p1.7) (p0.0-p0.7) (p3.0-p3.7) to adc2 input to external memory interface (emif) to adc0 input to comparators /sysclk cnvstr0 cnvstr2 c8051f040/1/2/3/4/5/6/7 30 rev. 1.5 1.5. programmable counter array the c8051f04x mcu family includes an on-board pr ogrammable counter/timer array (pca) in addition to the five 16-bit general purpose counter/timers. th e pca consists of a dedica ted 16-bit counter/timer time base with six programmable capture/compare m odules. the timebase is clocked from one of six sources: the system clock divided by 12, the system clock divided by 4, timer 0 overflow, an external clock input (eci pin), the system clock, or the external oscillator source divided by 8. each capture/compare module can be configured to operate in one of six modes: edge-triggered capture, software timer, high speed output, frequency output, 8-bit pulse width modulator, or 16-bit pulse width modulator. the pca capture/compare module i/o and external clock input are routed to the mcu port i/ o via the digital crossbar. figure 1.10. pca block diagram capture/compare module 1 capture/compare module 0 capture/compare module 2 capture/compare module 3 cex1 eci crossbar cex2 cex3 cex0 port i/o 16-bit counter/timer pca clock mux sysclk/12 sysclk/4 timer 0 overflow eci sysclk external clock/8 capture/compare module 4 cex4 capture/compare module 5 cex5 c8051f040/1/2/3/4/5/6/7 rev. 1.5 31 1.6. controller area network the c8051f04x family of devices feature a controlle r area network (can) controller that implements serial communication using the can protocol. the can controller facilit ates communication on a can net- work in accordance with the bosch sp ecification 2.0a (basic can) and 2.0b (full can). the can controller consists of a can core, message ram (separate from the c8051 ram), a message handler state machine, and control registers. the can controller can operate at bit rates up to 1 mbit/second. silicon labs can has 32 message objects each having its own identifier mask used for acceptance filtering of re ceived messages. incoming data, message objects and identifier masks are stored in the can message ram. all protocol functions for transmission of data and acceptance filtering is performed by the can controller and not by the c8051 mcu. in this way, minimal cpu bandwidth is used for can communication. the c8051 configures the can controller, accesses received data, and passes data for transmission via special function registers (sfr) in the c8051. figure 1.11. can c ontroller diagram 1.7. serial ports the c8051f04x mcu family includes two enhanced full-duplex uarts, an enhanced spi bus, and smbus/i 2 c. each of the serial buses is fully implemen ted in hardware and makes extensive use of the cip-51's interrupts, thus requiring very little intervention by the cpu. the serial buses do not "share" resources such as timers, interrupts, or port i/o, so any or all of the serial buses may be used together with any other. message handler registers message ram (32 message objects) can core tx rx can controller cip-51 mcu interrupt s f r 's cantx canrx c8051f04x s y s c l k can_clk (f sys ) brp prescaler c8051f040/1/2/3/4/5/6/7 32 rev. 1.5 1.8. 12/10-bit analog to digital converter the c8051f040/1 devices have an on-chip 12-bit sar adc (adc0) with a 9-chan nel input multiplexer and programmable gain amplifier. with a maximum throughput of 100 ksps, the adc offers true 12-bit per- formance with an inl of 1lsb. c8051f042/3/4/5/6/7 devices include a 10-bit sar adc with similar spec- ifications and configuration options . the adc0 voltage reference is se lected between the dac0 output and an external vref pin. on c8051f040/2/4/6 devi ces, adc0 has its own dedicated vref0 input pin; on c8051f041/3/5/7 devices, the adc0 uses the vr efa input pin and, on the c8051f041/3, shares it with the 8-bit adc2. the on-chip 15 ppm/c voltage reference may generate the voltage reference for the on-chip adcs or other system co mponents via the vref output pin. the adc is under full control of the cip-51 microcontroller via its associated special function registers. one input channel is tied to an internal temperatur e sensor, while the other eight channels are available externally. each pair of the eight external input channels can be configured as either two single-ended inputs or a single differential input. the system cont roller can also put the adc into shutdown mode to save power. a programmable gain amplifier follows the analog multiplexer. the gain can be set to 0.5, 1, 2, 4, 8, or 16 and is software programmable. the gain stage can be especially useful when di fferent adc input channels have widely varied input voltage signals, or when it is necessary to "zoom in" on a signal with a large dc offset (in differential mode, a dac coul d be used to provide the dc offset). conversions can be started in four ways; a software command, an overflow of ti mer 2, an overflow of timer 3, or an external signal input. this flexibility allows the start of c onversion to be tri ggered by software events, external hw signals, or a periodic timer overflow signal. conversion completions are indicated by a status bit and an interrupt (if enabled). the resulting 10 - or 12-bit data word is la tched into two sfrs upon completion of a conversion. the data can be right or left justified in these registers under software control. window compare registers for the adc data can be co nfigured to interrupt the controller when adc data is within or outside of a specified range. the adc ca n monitor a key voltage continuously in background mode, but not interrupt the controller unless the converted data is within the specified window. figure 1.12. 10/12-bit adc block diagram 12/10-bit sar adc 12 + - temp sensor + - + - 9-to-1 amux (se or diff) + - x ain0.0 ain0.1 ain0.2 ain0.3 av+ programmable gain amplifier analog multiplexer window compare logic adc data registers window compare interrupt conversion complete interrupt configuration, control, and data registers start conversion timer 3 overflow timer 2 overflow write to ad0busy cnvstr0 external vref pin dac0 output (c8051f040/1/2/3 only) vref agnd hvda hvain + hvain - port 3 pins c8051f040/1/2/3/4/5/6/7 rev. 1.5 33 1.9. 8-bit analog to digital c onverter (c8051f040/1/2/3 only) the c8051f040/1/2/3 devices have an on-board 8-bi t sar adc (adc2) with an 8-channel input multi- plexer and programmable gain amplifier. this adc fe atures a 500 ksps maximum throughput and true 8- bit performance with an inl of 1lsb. eight input pi ns are available for measurement and can be pro- grammed as single-ended or differential inputs. the ad c is under full control of the cip-51 microcontroller via the special function registers. the adc2 voltag e reference is selected between the analog power supply (av+) and an external vref pin. on c805 1f040/2 devices, adc2 has its own dedicated vref2 input pin; on c8051f041/3 devices, adc2 shares the vrefa input pin with the 12/10-bit adc0. user soft- ware may put adc2 into shutdown mode to save power. a programmable gain amplifier follows the analog multiplexer. the gain stage can be especially useful when different adc input channels have widely varied input voltage signals, or when it is necessary to "zoom in" on a signal with a large dc offset (in differ ential mode, a dac could be used to provide the dc off- set). the pga gain can be set in software to 0.5, 1, 2, or 4. a flexible conversion scheduling s ystem allows adc2 conv ersions to be initiated by software commands, timer overflows, or an external input signal. adc2 conversions may also be synchronized with adc0 soft- ware-commanded conversions. conversion completions ar e indicated by a status bit and an interrupt (if enabled), and the resulting 8-bit data word is latched into an sfr upon completion. figure 1.13. 8- bit adc diagram + - av+ 8 8-to-1 amux x ain2.0 ain2.1 ain2.2 ain2.3 ain2.4 ain2.5 ain2.6 ain2.7 configuration, control, and data registers programmable gain amplifier analog multiplexer 8-bit sar adc start conversion timer 3 overflow timer 2 overflow write to ad2busy cnvstr2 input write to ad0busy (synchronized with adc0) adc data register conversion complete interrupt external vref pin av+ vref single-ended or differential measurement + - + - + - + - window compare logic window compare interrupt c8051f040/1/2/3/4/5/6/7 34 rev. 1.5 1.10. comparators and dacs each c8051f040/1/2/3 mcu has two 12-bit dacs, and all c8051f04x devices have three comparators on chip. the mcu data and control interface to each co mparator and dac is via the special function regis- ters. the mcu can place any dac or comparator in low power shutdown mode. the comparators have software programmable hysteresis and response time. each comparator can gen- erate an interrupt on its rising edge, falling edge, or both; these interrupts are capable of waking up the mcu from sleep mode. the comparators' output state can also be polled in software. the comparator out- puts can be programmed to appear on the port i/o pins via the crossbar. the dacs are voltage output mode and include a flex ible output scheduling mechanism. this scheduling mechanism allows dac output updates to be forced by a software write or a timer 2, 3, or 4 overflow. the dac voltage reference is supplied via the dedicated vrefd input pin on c8051f040/2 devices or via the internal voltage reference on c8051f041/3 devices. t he dacs are especially useful as references for the comparators or offsets for the differential inputs of the adc. figure 1.14. comparat or and dac diagram + - cpn+ cpn- dac0 dac1 vref vref cip-51 and interrupt handler cpn dac0 dac1 cpn output (port i/o) sfr's (data and cntrl) crossbar 3 comparators comparator inputs port 2.[7:2] (c8051f040/1/2/3 only) (c8051f040/1/2/3 only) c8051f040/1/2/3/4/5/6/7 rev. 1.5 35 2. absolute maximum ratings table 2.1. absolute maximum ratings* parameter conditions min typ max units ambient temperature under bias ?55 ? 125 c storage temperature ?65 ? 150 c voltage on any pin (except v dd , port i/o, and jtag pins) with respect to dgnd ?0.3 ? v dd + 0.3 v voltage on any port i/o pin, /rst, and jtag pins with respect to dgnd ?0.3 ? 5.8 v voltage on v dd with respect to dgnd ?0.3 ? 4.2 v maximum total current through v dd , av+, dgnd, and agnd ?? 800ma maximum output current sunk by any port pin ? ? 100 ma maximum output current sunk by any other i/o pin ? ? 50 ma maximum output current sourced by any port pin ? ? 100 ma maximum output current sourced by any other i/o pin ? ? 50 ma *note: stresses above those listed under ?absolute maximu m ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of th e devices at those or any other conditions above those indicated in the operation listings of th is specification is not implied. exposure to maximum rating conditions for extended periods may affect device reliability. ? ? due to special i/o design requirements of the high voltage dif ference amplifier, undue electrical over-voltage stress (i.e., esd) experienced by these pads may result in impedance degradation of these inputs (hvain+ and hvain?). for this reason, care should be taken to ensure proper handling and use as typically required to prevent esd damage to electrostatica lly sensitive cmos devices (e.g., static-free workstations, use of grounding straps, over-voltage protec tion in end-applications, etc.) c8051f040/1/2/3/4/5/6/7 36 rev. 1.5 3. global dc elect rical characteristic table 3.1. global dc electrical characteristics ?40 to +85 c, 25 mhz system clock unless otherwise specified. parameter conditions min typ max units analog supply voltage 1 2.7 3.0 3.6 v analog supply current internal ref, adc, dac, com- parators all active ?1.7?ma analog supply current with analog sub-systems inactive internal ref, adc, dac, com- parators all disabled, oscillator disabled ?0.2?a analog-to-digital supply delta (|v dd - av+|) ??0.5v digital supply voltage 2.7 3.0 3.6 v digital supply current with cpu active ? (normal mode) v dd = 2.7 v, clock = 25 mhz ? v dd = 2.7 v, clock = 1 mhz ? v dd = 2.7 v, clock = 32 khz ? ? ? 10 0.5 20 ? ? ? ma ma a digital supply current with cpu inactive (not accessing flash) (idle mode) v dd = 2.7 v, clock = 25 mhz ? v dd = 2.7 v, clock = 1 mhz ? v dd = 2.7 v, clock = 32 khz ? ? ? 5 0.2 10 ? ? ? ma ma a digital supply current (shutdown) (stop mode) oscillator not running ? 0.2 ? a digital supply ram data retention voltage ?1.5? v specified operating temperature range ?40 ? +85 c sysclk (system clock frequency) 2 0?25mhz tsysl (sysclk low time) 18 ? ? ns tsysh (sysclk high time) 18 ? ? ns notes: 1. anal og supply av+ must be greater than 1 v for v dd monitor to operate. 2. sysclk m ust be at least 32 khz to enable debugging. c8051f040/1/2/3/4/5/6/7 rev. 1.5 37 4. pinout and package definitions table 4.1. pin definitions name pin numbers type description f040/2/4/6 f041/3/5/7 v dd 37, 64, 90 24, 41, 57 digital supply voltage. must be tied to +2.7 to +3.6 v. dgnd 38, 63, 89 25, 40, 56 digital ground. must be tied to ground. av+ 8, 11, 14 3, 6 analog supply voltage. must be tied to +2.7 to +3.6 v. agnd 9, 10, 13 4, 5 analog ground. must be tied to ground. tms 1 58 d in jtag test mode select with internal pullup. tck 2 59 d in jtag test clock with internal pullup. tdi 3 60 d in jtag test data input with inte rnal pullup. tdi is latched on the rising edge of tck. tdo 4 61 d out jtag test data output with internal pullup. data is shif ted out on tdo on the fa lling edge of tck. tdo out - put is a tri-state driver. /rst 5 62 d i/o device reset. open-drain outpu t of internal v dd monitor. is driven low when v dd is < 2.7 v and monen is high. an ex ternal source can initiate a system reset by driving this pin low. xtal1 26 17 a in crystal input. this pin is the return for the internal oscilla - tor circuit for a crystal or ceramic resonator. for a preci - sion internal clock, connect a crystal or ceramic resonator from xtal1 to xtal2. if overdriven by an external cmos clock, this becomes the system clock. xtal2 27 18 a out crystal output. this pin is the excitation driver for a crystal or ceramic resonator. monen 28 19 d in v dd monitor enable. when tied high, this pin enables the internal v dd monitor, which forces a system reset when v dd is < 2.7 v. when tied low, the internal v dd monitor is disabled. ? in most applications, monen should be connected di rectly to v dd . vref 12 7 a i/o bandgap voltage reference output (all devices). dac voltage reference input (c8051f041/3 only). vrefa 8 a in adc0 (c8051f041/3/5/7) and adc2 (c8051f041/3 only) ? voltage reference input. vref0 16 a in adc0 voltage reference input. vref2 17 a in adc2 voltage reference input (c8051f040/2 only). vref 15 a in dac voltage reference input (c8051f040/2 only). ain0.0 18 9 a in adc0 input channel 0 (see adc0 specification for com - plete description). c8051f040/1/2/3/4/5/6/7 38 rev. 1.5 ain0.1 19 10 a in adc0 input channel 1 (see adc0 specification for com - plete description). ain0.2 20 11 a in adc0 input channel 2 (see adc0 specification for com - plete description). ain0.3 21 12 a in adc0 input channel 3 (see adc0 specification for com - plete description). hvcap 22 13 a i/o high voltage difference amplifier capacitor. hvref 23 14 a in high voltage difference amplifier bias reference. hvain+ 24 15 a in high voltage difference amp lifier positive signal input. hvain- 25 16 a in high voltage difference amplif ie r negative signal input. cantx 7 2 d out controller area network transmit output. canrx 6 1 d in controller area network receive input. dac0 100 64 a out digital to analog converter 0 voltage output. (see dac s pecification for complete de scription). (c8 051f040/1/2/3 only) dac1 99 63 a out digital to analog converter 1 voltage output. (see dac s pecification for complete de scription). (c8 051f040/1/2/3 only) p0.0 62 55 d i/o port 0.0. see port input/output section for complete de scription. p0.1 61 54 d i/o port 0.1. see port input/output section for complete de scription. p0.2 60 53 d i/o port 0.2. see port input/output section for complete de scription. p0.3 59 52 d i/o port 0.3. see port input/output section for complete de scription. p0.4 58 51 d i/o port 0.4. see port input/output section for complete de scription. p0.5/ale 57 50 d i/o ale strobe for external memory address bus (multi - plexed mode) port 0.5 see port input/output section for complete description. p0.6/rd 56 49 d i/o /rd strobe for external memory address bus port 0.6 see port input/output section for complete description. p0.7/wr 55 48 d i/o /wr strobe for external memory address bus port 0.7 see port input/output section for complete description. table 4.1. pin definitions (continued) name pin numbers type description f040/2/4/6 f041/3/5/7 c8051f040/1/2/3/4/5/6/7 rev. 1.5 39 p1.0/ain2.0/a8 36 29 a in d i/o adc1 input channel 0 (see adc1 specification for com - plete description). bit 8 external memory address bus (non-multiplexed mo de) port 1.0 see port input/output section for complete description. p1.1/ain2.1/a9 35 28 a in d i/o port 1.1. see port input/output section for complete de scription. p1.2/ain2.2/ a10 34 27 a in d i/o port 1.2. see port input/output section for complete de scription. p1.3/ain2.3/ a1 1 33 26 a in d i/o port 1.3. see port input/output section for complete de scription. p1.4/ain2.4/ a12 32 23 a in d i/o port 1.4. see port input/output section for complete de scription. p1.5/ain2.5/ a13 31 22 a in d i/o port 1.5. see port input/output section for complete de scription. p1.6/ain2.6/ a14 30 21 a in d i/o port 1.6. see port input/output section for complete de scription. p1.7/ain2.7/ a15 29 20 a in d i/o port 1.7. see port input/output section for complete de scription. p2.0/a8m/a0 46 37 d i/o bit 8 external memory address bus (multiplexed mode) bit 0 external memory address bus (non-multiplexed mo de) port 2.0 see port input/output section for complete description. p2.1/a9m/a1 45 36 d i/o port 2.1. see port input/output section for complete de scription. p2.2/a10m/a2 44 35 d i/o port 2.2. see port input/output section for complete de scription. p2.3/a11m/a3 43 34 d i/o port 2.3. see port input/output section for complete de scription. p2.4/a12m/a4 42 33 d i/o port 2.4. see port input/output section for complete de scription. p2.5/a13m/a5 41 32 d i/o port 2.5. see port input/output section for complete de scription. p2.6/a14m/a6 40 31 d i/o port 2.6. see port input/output section for complete de scription. p2.7/a15m/a7 39 30 d i/o port 2.7. see port input/output section for complete de scription. table 4.1. pin definitions (continued) name pin numbers type description f040/2/4/6 f041/3/5/7 c8051f040/1/2/3/4/5/6/7 40 rev. 1.5 p3.0/ad0/d0 54 47 a in d i/o bit 0 external memory address/data bus (multiplexed mo de) bit 0 external memory data bus (non-multiplexed mode) port 3.0 see port input/output section for complete description. adc0 input. (see adc0 s pecification for complete description.) p3.1/ad1/d1 53 46 a in d i/o port 3.1. see port input/output section for complete de scription. adc0 input. (see adc0 s pecification for complete description.) p3.2/ad2/d2 52 45 a in d i/o port 3.2. see port input/output section for complete de scription. adc0 input. (see adc0 s pecification for complete description.) p3.3/ad3/d3 51 44 a in d i/o port 3.3. see port input/output section for complete de scription. adc0 input. (see adc0 s pecification for complete description.) p3.4/ad4/d4 50 43 a in d i/o port 3.4. see port input/output section for complete de scription. adc0 input. (see adc0 s pecification for complete description.) p3.5/ad5/d5 49 42 a in d i/o port 3.5. see port input/output section for complete de scription. adc0 input. (see adc0 s pecification for complete description.) p3.6/ad6/d6 48 39 a in d i/o port 3.6. see port input/output section for complete de scription. adc0 input. (see adc0 s pecification for complete description.) p3.7/ad7/d7 47 38 a in d i/o port 3.7. see port input/output section for complete de scription. adc0 input. (see adc0 s pecification for complete description.) p4.0 98 d i/o port 4.0. see port input/output section for complete de scription. p4.1 97 d i/o port 4.1. see port input/output section for complete de scription. p4.2 96 d i/o port 4.2. see port input/output section for complete de scription. p4.3 95 d i/o port 4.3. see port input/output section for complete de scription. table 4.1. pin definitions (continued) name pin numbers type description f040/2/4/6 f041/3/5/7 c8051f040/1/2/3/4/5/6/7 rev. 1.5 41 p4.4 94 d i/o port 4.4. see port input/output section for complete de scription. p4.5/ale 93 d i/o ale strobe for external memory address bus (multi - plexed mode) port 4.5 see port input/output section for complete description. p4.6/rd 92 d i/o /rd strobe for external memory address bus port 4.6 see port input/output section for complete description. p4.7/wr 91 d i/o /wr strobe for external memory address bus port 4.7 see port input/output section for complete description. p5.0/a8 88 d i/o bit 8 external memory address bus (non-multiplexed mo de) port 5.0 see port input/output section for complete description. p5.1/a9 87 d i/o port 5.1. see port input/output section for complete de scription. p5.2/a10 86 d i/o port 5.2. see port input/output section for complete de scription. p5.3/a11 85 d i/o port 5.3. see port input/output section for complete de scription. p5.4/a12 84 d i/o port 5.4. see port input/output section for complete de scription. p5.5/a13 83 d i/o port 5.5. see port input/output section for complete de scription. p5.6/a14 82 d i/o port 5.6. see port input/output section for complete de scription. p5.7/a15 81 d i/o port 5.7. see port input/output section for complete de scription. p6.0/a8m/a0 80 d i/o bit 8 external memory address bus (multiplexed mode) bit 0 external memory address bus (non-multiplexed mo de) port 6.0 see port input/output section for complete description. p6.1/a9m/a1 79 d i/o port 6.1. see port input/output section for complete de scription. p6.2/a10m/a2 78 d i/o port 6.2. see port input/output section for complete de scription. p6.3/a11m/a3 77 d i/o port 6.3. see port input/output section for complete de scription. table 4.1. pin definitions (continued) name pin numbers type description f040/2/4/6 f041/3/5/7 c8051f040/1/2/3/4/5/6/7 42 rev. 1.5 p6.4/a12m/a4 76 d i/o port 6.4. see port input/output section for complete de scription. p6.5/a13m/a5 75 d i/o port 6.5. see port input/output section for complete de scription. p6.6/a14m/a6 74 d i/o port 6.6. see port input/output section for complete de scription. p6.7/a15m/a7 73 d i/o port 6.7. see port input/output section for complete de scription. p7.0/ad0/d0 72 d i/o bit 0 external memory address/data bus (multiplexed mo de) bit 0 external memory data bus (non-multiplexed mode) port 7.0 see port input/output section for complete description. p7.1/ad1/d1 71 d i/o port 7.1. see port input/output section for complete de scription. p7.2/ad2/d2 70 d i/o port 7.2. see port input/output section for complete de scription. p7.3/ad3/d3 69 d i/o port 7.3. see port input/output section for complete de scription. p7.4/ad4/d4 68 d i/o port 7.4. see port input/output section for complete de scription. p7.5/ad5/d5 67 d i/o port 7.5. see port input/output section for complete de scription. p7.6/ad6/d6 66 d i/o port 7.6. see port input/output section for complete de scription. p7.7/ad7/d7 65 d i/o port 7.7. see port input/output section for complete de scription. table 4.1. pin definitions (continued) name pin numbers type description f040/2/4/6 f041/3/5/7 c8051f040/1/2/3/4/5/6/7 rev. 1.5 43 figure 4.1. tqfp-1 00 pinout diagram c8051f040/2/4/6 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 42 43 44 45 46 47 48 49 50 1 2 3 4 5 6 7 8 9 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 75 74 73 72 71 70 69 68 67 p7.6/ad6/d6 p7.7/ad7/d7 vdd dgnd p0.0 p0.1 p0.2 p0.3 p0.4 p0.5/ale p0.6/rd p0.7/wr p3.0/ad0/d0 p3.1/ad1/d1 p3.2/ad2/d2 p3.3/ad3/d3 p6.5/a13m/a5 p6.6/a14m/a6 p6.7/a15m/a7 p7.0/ad0/d0 p7.1/ad1/d1 p7.2/ad2/d2 p7.3/ad3/d3 p7.4/ad4/d4 p7.5/ad5/d5 dac0 dac1 p4.0 p4.1 p4.2 p4.3 p4.4 p4.5/ale p4.6/rd p4.7/wr vdd dgnd p5.0/a8 p5.1/a9 p5.2/a10 p5.3/a11 p5.4/a12 p5.5/a13 p5.6/a14 p5.7/a15 p6.0/a8m/a0 p6.1/a9m/a1 p6.2/a10m/a2 p6.3/a11m/a3 p6.4/a12m/a4 agnd av+ vref agnd av+ vrefd vref0 vref2 ain0.0 ain0.1 ain0.2 ain0.3 hvcap hvref hvain+ hvain- tms tck tdi tdo /rst canrx cantx av+ agnd xtal1 xtal2 monen p1.7/ain2.7/a15 p1.6/ain2.6/a14 p1.5/ain2.5/a13 p1.4/ain2.4/a12 vdd dgnd p1.3/ain2.3/a11 p1.2/ain2.2/a10 p1.1/ain2.1/a9 p1.0/ain2.0/a8 p2.7/a15m/a7 p2.6/a14m/a6 p2.5/a13m/a5 p2.4/a12m/a4 p2.3/a11m/a3 p2.2/a10m/a2 p2.1/a9m/a1 p2.0/a8m/a0 p3.7/ad7/d7 p3.6/ad6/d6 p3.5/ad5/d5 p3.4/ad4/d4 c8051f040/1/2/3/4/5/6/7 44 rev. 1.5 figure 4.2. tqfp-1 00 package drawing a a1 a2 b d d1 e e e1 l - 0.05 0.95 0.17 - - - - - 0.45 - - 1.00 0.22 16.00 14.00 0.50 16.00 14.00 0.60 1.20 0.15 1.05 0.27 - - - - - 0.75 min (mm) nom (mm) max (mm) 100 e a1 b a2 a pin 1 designator 1 e1 e d1 d l c8051f040/1/2/3/4/5/6/7 rev. 1.5 45 figure 4.3. tqfp- 64 pinout diagram c8051f041/3/5/7 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 dac0 dac1 /rst tdo tdi tck tms vdd dgnd p0.0 p0.1 p0.2 p0.3 p0.4 p0.5/ale p0.6/rd p0.7/wr p3.0/ad0/d0 p3.1/ad1/d1 p3.2/ad2/d2 p3.3/ad3/d3 p3.4/ad4/d4 p3.5/ad5/d5 vdd dgnd p3.6/ad6/d6 p3.7/ad7/d7 p2.0/a8m/a0 p2.1/a9m/a1 p2.2/a10m/a2 p2.3/a11m/a3 p2.4/a12m/a4 canrx cantx av+ agnd agnd av+ vref vrefa ain0.0 ain0.1 ain0.2 ain0.3 hvcap hvref hvain+ hvain- xtal1 xtal2 monen p1.7/ain2.7/a15 p1.6/ain2.6/a14 p1.5/ain2.5/a13 p1.4/ain2.4/a12 vdd dgnd p1.3/ain2.3/a11 p1.2/ain2.2/a10 p1.1/ain2.1/a9 p1.0/ain2.0/a8 p2.7/a15m/a7 p2.6/a14m/a6 p2.5/a13m/a5 c8051f040/1/2/3/4/5/6/7 46 rev. 1.5 figure 4.4. tqfp- 64 package drawing a a1 a2 b d d1 e e e1 l - 0.05 0.95 0.17 - - - - - 0.45 - - - 0.22 12.00 10.00 0.50 12.00 10.00 0.6 1.20 0.15 1.05 0.27 - - - - - 0.75 min (mm) nom (mm) max (mm) 1 64 e e1 e a1 b d d1 pin 1 designator a2 a l c8051f040/1/2/3/4/5/6/7 rev. 1.5 47 5. 12-bit adc (adc0, c8051f040/1 only) the adc0 subsystem for the c8051f040/1 consists of a 9-channel, configurable analog multiplexer (amux0), a programmable gain amplifier (pga0), a nd a 100 ksps, 12-bit successive-approximation-regis- ter adc with integrated track-and-hold and programmable window detector (see block diagram in figure 5.1). the amux0, pga0, data conversion mode s, and window detector are all configurable under software control via the special fu nction registers shown in figure 5. 1. the voltage reference used by adc0 is selected as described in section ?9. voltage reference (c8051f040/2/4/6)? on page 113 for c8051f040 devices, or section ?10. voltage reference (c8051f041/3/5/7)? on page 117 for c8051f041 devices. the adc0 subsystem (adc0, trac k-and-hold and pga0) is enabled only when the ad0en bit in the adc0 cont rol register (adc0cn) is set to logic 1. the adc0 subsystem is in low power shutdown when this bit is logic 0. figure 5.1. 12-bit adc0 functional block diagram 5.1. analog multiplexer and pga the analog multiplexer can input analog signals to the adc from four external analog input pins (ain0.0 - ain0.3), port 3 port pins (optionally configured as anal og input pins), high voltage difference amplifier, or an internally connected on-chip temperature sensor (tem perature transfer function is shown in figure 5.6). amux input pairs can be programmed to operate in either differential or single-ended mode. this allows the user to select the best measurement technique for each input channel, and even accommodates mode changes "on-the-fly". the amux defaults to all single-ended inputs upon reset. there are three registers associated with the amux: the channel selection regist er amx0sl (sfr definition 5.2), the configuration register amx0cf (sfr definition 5.1), and the port pi n selection register amx0prt (sfr definition 5.3). table 5.1 shows amux functionality by channel for ea ch possible configuratio n. the pga amplifies the amux output signal by an amount determined by the states of the amp0gn2-0 bi ts in the adc0 configu- ration register, adc0cf (sfr definition 5.5). the pga can be software-programmed for gains of 0.5, 2, 4, 8 or 16. gain defaults to unity on reset. 12-bit sar adc ref + - av+ temp sensor 12 9-to-1 amux (se or diff) av+ 24 12 ad0en sysclk x start conversion agnd amx0cf adc0l adc0h adc0ltl adc0lth adc0gtl adc0gth amx0sl amx0ad0 amx0ad1 amx0ad2 amx0ad3 ain01ic ain23ic hvdaic port3ic adc0cf amp0gn0 amp0gn1 amp0gn2 ad0sc0 ad0sc1 ad0sc2 ad0sc3 ad0sc4 adc0cn ad0ljst ad0wint ad0cm0 ad0cm1 ad0busy ad0int ad0tm ad0en timer 3 overflow 00 01 10 11 ad0busy (w) cnvstr0 ad0wint comb. logic hv input port 3 i/o pins analog input pins agnd timer 2 overflow c8051f040/1/2/3/4/5/6/7 48 rev. 1.5 5.1.1. analog input configuration the analog multiplexer routes signals from exter nal analog input pins, port 3 i/o pins (see section ?17.1.5. configuring port 1, 2, an d 3 pins as analog inputs? on page 207 ), a high voltage difference amplifier, and an on-chip temperature sensor as shown in figure 5.2. figure 5.2. analog input diagram analog signals may be input from four external analog input pins (ain0.0 through ain0.3) as differential or single-ended measurements. additionally, port 3 i/o po rt pins may be configured to input analog signals. port 3 pins configured as analog inputs are selected using the port pin selection register (amx0prt). any number of port 3 pins may be selected simultaneously as inputs to the amux. even numbered port 3 pins and odd numbered port 3 pins are routed to separate amux inputs. ( note: even port pins and odd port pins that are simultaneously selected will be shorted toge ther as ?wired-or?.) in this way, differential mea- surements may be made when using the port 3 pins (voltage difference between selected even and odd port 3 pins) as shown in figure 5.2. the high voltage differe nce amplifier (hvda) will acce pt analog input signals a nd reject up to 60 volts common-mode for differential measurement of up to the reference voltage to the adc (0 to vref volts). the output of the hvda can be selected as an input to the adc using the amux as any other channel is selected for input. (see section ?5.2. high-voltage differ ence amplifier? on page 52 ). + - + - + - 9-to-1 amux (se or diff) amx0cf ain01ic ain23ic hvdaic port3ic 12-bit sar adc x temp sensor agnd ain0.0 ain0.1 ain0.2 ain0.3 amx0sl amx0ad0 amx0ad1 amx0ad2 amx0ad3 0 7 6 5 4 3 2 1 8 hv amp hvcap hvref hvain - hvain + p3.6 p3.4 p3.2 p3.0 p3.7 p3.5 p3.3 p3.1 (wired-or) (wired-or) amx0prt pain0en pain2en pain4en pain6en pain7en pain5en pain3en pain1en p3even p3odd + - c8051f040/1/2/3/4/5/6/7 rev. 1.5 49 sfr definition 5.1. amx0cf: amux0 configuration sfr definition 5.2. amx0sl: amux0 channel select bits7-4: unused. read = 0000b; write = don?t care bit3: port3ic: port 3 even/odd pin input pair configuration bit 0: port 3 even and odd input channels are independent single-ended inputs 1: port 3 even and odd input channels are (respectively) +, - difference input pair bit2: hvda2c: hvda 2?s compliment bit 0: hvda output measured as an independent single-ended input 1: hvda result for 2?s compliment value bit1: ain23ic: ain0.2, ain0.3 input pair configuration bit 0: ain0.2 and ain0.3 are independent single-ended inputs 1: ain0.2, ain0.3 are (respectively) +, - difference input pair bit0: ain01ic: ain0.0, ain0.1 input pair configuration bit 0: ain0.0 and ain0.1 are independent single-ended inputs 1: ain0.0, ain0.1 are (respectively) +, - difference input pair note: the adc0 data word is in 2?s complement format for channels configured as difference. r r r r r/w r/w r/w r/w reset value - - - - port3ic hvda2c ain23ic ain01ic 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: sfr address: sfr page: 0xba 0 bits7-4: unused. read = 0000b; write = don?t care bits3-0: amx0ad3-0: amx0 address bits 0000-1111b: adc inputs selected per table 5.1. r r r r r/w r/w r/w r/w reset value - - - - amx0ad3 amx0ad2 amx0ad1 amx0ad0 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: sfr page: 0xbb 0 c8051f040/1/2/3/4/5/6/7 50 rev. 1.5 note: ?p3even? denotes even numbered and ?p3odd? odd numbered port 3 pins selected in the amx0prt register. table 5.1. amux selection chart (amx0ad3?0 and amx0cf3?0 bits) amx0ad3-0 0000 0001 0010 0011 0100 0101 0110 0111 1xxx amx0cf bits 3-0 0000 ain0.0 ain0.1 ain0.2 ain0.3 hvda agnd p3even p3odd temp senso r 0001 +(ain0.0) -(ain0.1) ain0.2 ain0.3 hvda agnd p3even p3odd temp senso r 0010 ain0.0 ain0.1 +(ain0.2) -(ain0.3) hvda agnd p3even p3odd temp senso r 0011 +(ain0.0) -(ain0.1) +(ain0.2) -(ain0.3) hvda agnd p3even p3odd temp senso r 0100 ain0.0 ain0.1 ain0.2 ain0.3 +(hvda) -(hvref) p3even p3odd temp senso r 0101 +(ain0.0) -(ain0.1) ain0.2 ain0.3 +(hvda) -(hvref) p3even p3odd temp senso r 0110 ain0.0 ain0.1 +(ain0.2) -(ain0.3) +(hvda) -(hvref) p3even p3odd temp senso r 0111 +(ain0.0) -(ain0.1) +(ain0.2) -(ain0.3) +(hvda) -(hvref) p3even p3odd temp senso r 1000 ain0.0 ain0.1 ain0.2 ain0.3 hvda agnd +p3even -p3odd temp senso r 1001 +(ain0.0) -(ain0.1) ain0.2 ain0.3 hvda agnd +p3even -p3odd temp senso r 1010 ain0.0 ain0.1 +(ain0.2) -(ain0.3) hvda agnd +p3even -p3odd temp senso r 1011 +(ain0.0) -(ain0.1) +(ain0.2) -(ain0.3) hvda agnd +p3even -p3odd temp senso r 1100 ain0.0 ain0.1 ain0.2 ain0.3 +(hvda) -(hvref) +p3even -p3odd) temp senso r 1101 +(ain0.0) -(ain0.1) ain0.2 ain0.3 +(hvda) -(hvref) +p3even -p3odd temp senso r 1110 ain0.0 ain0.1 +(ain0.2) -(ain0.3) +(hvda) -(hvref) +p3even -p3odd temp senso r 1111 +(ain0.0) -(ain0.1) +(ain0.2) -(ain0.3) +(hvda) -(hvref) +p3even -p3odd temp senso r c8051f040/1/2/3/4/5/6/7 rev. 1.5 51 sfr definition 5.3. amx0prt: port 3 pin selection bit7: pain7en: pin 7 analog input enable bit 0: p3.7 is not selected as an analog input to the amux. 1: p3.7 is selected as an analog input to the amux. bit6: pain6en: pin 6 analog input enable bit 0: p3.6 is not selected as an analog input to the amux. 1: p3.6 is selected as an analog input to the amux. bit5: pain5en: pin 5 analog input enable bit 0: p3.5 is not selected as an analog input to the amux. 1: p3.5 is selected as an analog input to the amux. bit4: pain4en: pin 4 analog input enable bit 0: p3.4 is not selected as an analog input to the amux. 1: p3.4 is selected as an analog input to the amux. bit3: pain3en: pin 3 analog input enable bit 0: p3.3 is not selected as an analog input to the amux. 1: p3.3 is enabled as an analog input to the amux. bit2: pain2en: pin 2 analog input enable bit 0: p3.2 is not selected as an analog input to the amux. 1: p3.2 is enabled as an analog input to the amux. bit1: pain1en: pin 1 analog input enable bit 0: p3.1 is not selected as an analog input to the amux. 1: p3.1 is enabled as an analog input to the amux. bit0: pain0en: pin 0 analog input enable bit 0: p3.0 is not selected as an analog input to the amux. 1: p3.0 is enabled as an analog input to the amux. note: any number of port 3 pins may be selected simultaneously inputs to the amux. odd numbered and even numbered pins that are selected simultaneous ly are shorted together as ?wired-or?. r/w r/w r/w r/w r/w r/w r/w r/w reset value pain7en pain6en pain5en pain4en pain 3en pain2en pain1en pain0en 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: sfr page: 0xbd 0 c8051f040/1/2/3/4/5/6/7 52 rev. 1.5 5.2. high-voltage difference amplifier the high voltage difference amplifier (hvda) can be used to measure high differential voltages up to 60 v peak-to-peak, reject high common-mode voltages up to 60 v, and condition the signal voltage range to be suitable for input to adc0. the input signal to the hvda may be below agnd to ?60 volts, and as high as +60 volts, making the device suitable for both single and dual supply applications. the hvda provides a common-mode signal for the adc via the high voltage reference input (hvref), allowing measurement of signals outside the specified adc input range using on-chip circuitry. the hvda has a gain of 0.05 v/v to 14 v/v. the first stage 20:1 difference amplifier has a gain of 0.05 v/v when the output amplifier is used as a unity gain buffer. when the output amplifier is set to a gain of 280 (selected using the hvgain bits in the high voltage control register), an overall gain of 14 can be attained. the hvda uses four available external pins: +hva in, ?hvain, hvcap, and hvref. hvain+ and hvain- serve as the differential inputs to the hvda. hvref should be used to provide a common mode reference for input to adc0, and to prevent the output of the hvda circuit from saturating. th e output from the hvda circuit as calculated by equation 5.1 must re main within the ?output voltage range? specification listed in table 5.3. the ideal value for hvref in most applications is equal to 1/2 the supply voltage for the device. when the adc is configured for differential measurement, the hvref signal is applied to the ain- input of the adc, thereby removing hvref from the measurement. hvcap facilitates the use of a capac- itor for noise filtering in conjuncti on with r7 (see figure 5.3 for r7 and other approximate resistor values). alternatively, the hvcap could also be used to access amplification of the first stage of the hvda at an external pin. (see table 5.3 on page 68 fo r electrical specifications of the hvda.) equation 5.1. calculating hvda output voltage to ain+ figure 5.3. high voltage differen ce amplifier functional diagram v out hvain + ?? hvain - ?? ? ?? gain hvref + ? = note: the output voltage of the hvda is selected as an input to the ain+ input of adc0 via its analog multiplexer (amux0). hvda output voltages outside the adc?s input ra nge will result in saturation of the adc input. allow for adequate settle/tracking time for proper voltage measurements. ??? k ? 5k ? 100k ? 5k ? hva0cn gain setting hvain- hvain+ hvref hvcap vout (to amux0) 5k ? c8051f040/1/2/3/4/5/6/7 rev. 1.5 53 sfr definition 5.4. hva0cn: high voltage differ ence amplifier control bit7: hvdaen: high voltage difference amplifier (hvda) enable bit. 0: the hvda is disabled. 1: the hvda is enabled. bits6-3: reserved. bits2-0: hvgain3-hvgain0: hvda gain control bits. hvda gain control bits set the amplification gain if the difference signal input to the hvda as defined in the table below: r/w r r r r/w r/w r/w r/w reset value hvdaen - - - hvgain3 hvgain2 hvgain1 hvgain0 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: sfr page: 0xd6 0 hvgain3:hvgain0 hvda gain 0000 0.05 0001 0.1 0010 0.125 0011 0.2 0100 0.25 0101 0.4 0110 0.5 0111 0.8 1000 1.0 1001 1.6 1010 2.0 1011 3.2 1100 4.0 1101 6.2 1110 7.6 1111 14 c8051f040/1/2/3/4/5/6/7 54 rev. 1.5 5.3. adc modes of operation adc0 has a maximum conver sion speed of 100 ksps. the adc0 conversion clock is derived from the sys- tem clock divided by the va lue held in the adc0sc bits of register adc0cf. 5.3.1. starting a conversion a conversion can be initiated in one of four ways, depending on the programmed states of the adc0 start of conversion mode bits (ad0cm1, ad0cm0) in adc0cn. conversions ma y be initiated by the following: ? writing a ?1? to the ad0busy bit of adc0cn; ? a timer 3 overflow (i.e., ti me d continuous conversions); ? a rising edge detected on the external adc convert start signal, cnvstr0; ? a timer 2 overflow (i.e., ti me d continuous conversions). the ad0busy bit is set to logic 1 during conversion and re stored to logic 0 when conversion is complete. the falling edge of ad0busy triggers an interrupt (when en abled) and sets the ad 0int interrupt flag (adc0cn.5). converted data is available in the adc0 data word msb and lsb r egisters, adc0 h, adc0l. converted data can be either left or right justifie d in the adc0h:adc0l register pair (see example in figure 5.7) depending on the programmed state of the ad0ljst bit in the adc0cn register. when initiating conversions by writ ing a ?1? to ad0busy, the ad0int bit should be polled to determine when a conversion has completed (adc0 interrupts may also be us ed). the recommen ded polling proce- dure is shown below. step 1. write a ?0? to ad0int; step 2. write a ?1? to ad0busy; step 3. poll ad0int for ?1?; step 4. process adc0 data. 5.3.2. tracking modes according to table 5.2, each adc0 conversion must be preceded by a minimum tracking time for the con- verted result to be accurate. the ad0tm bit in register adc0cn controls the adc0 track-and-hold mode. in its default state, the adc0 input is continuously tracked when a conversion is not in progress. when the ad0tm bit is logic 1, adc0 operat es in low-power tracking mode. in this mode, each conversion is pre- ceded by a tracking period of 3 sar clocks after th e start-of-conversion signal. when the cnvstr0 signal is used to initiate conversions in low-power tracking mode, adc0 tra cks only when cnvstr0 is low; con- version begins on the rising edge of cnvstr0 (see figure 5.4). tracking can also be disabled when the entire chip is in low power standby or sleep mode s. low-power tracking mode is also useful when amux or pga settings are frequently changed, to ensure that settling time requirements are met (see section ?5.3.3. settling time requirements? on page 56 ). c8051f040/1/2/3/4/5/6/7 rev. 1.5 55 figure 5.4. 12-bit adc track and conversion example timing 123456789 1 0 1 1 1 2 1 3 1 4 1 5 1 6 cnvstr (ad0cm[1:0]=10) adc0tm=1 adc0tm=0 timer 2, timer 3 overflow; write '1' to ad0busy (ad0cm[1:0]=00, 01, 11) adc0tm=1 adc0tm=0 a. adc timing for external trigger source b. adc timing for internal trigger sources sar clocks sar clocks 123456789 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 123456789 1 0 1 1 1 2 1 3 1 4 1 5 1 6 sar clocks track convert low power mode low power or convert track or convert convert track track convert low power mode low power or convert track or convert convert track c8051f040/1/2/3/4/5/6/7 56 rev. 1.5 5.3.3. settling time requirements a minimum tracking time is required before an accurate conversion can be performe d. this tracking time is determined by the adc0 mux resistance, the adc0 sampling capacitance, any external source resis- tance, and the accuracy required fo r the conversion. figure 5.5 shows th e equivalent adc0 input circuits for both differential and single-ended modes. notice that the equivalent time constant for both input circuits is the same. the required settling ti me for a given settling accuracy ( sa ) may be approximated by equation 5.2. when measuring the temperature sensor output, r total reduces to r mux . note that in low-power tracking mode, three sar clocks are used for tracking at the start of every conversion. for most applications, these three sar clocks will meet the tracking r equirements. see table 5.2 for absolute minimum settling/tracking time requirements. equation 5.2. adc0 settling time requirements where: sa is the settling accuracy, given as a fraction of an lsb (for example, 0.25 to settle within 1/4 lsb) t is the r equired settling time in seconds r total is the sum of the adc0 mux resistanc e and any external source resistance. n is the ad c resolution in bits (12). figure 5.5. adc0 eq uivalent input circuits t 2 n sa ------ - ?? ?? r total c sample ? r mux = 5k rc input = r mux * c sample r mux = 5k c sample = 10pf c sample = 10pf mux select mux select differential mode ain0.x ain0.y r mux = 5k c sample = 10pf rc input = r mux * c sample mux select single-ended mode ain0.x c8051f040/1/2/3/4/5/6/7 rev. 1.5 57 figure 5.6. temperature sensor transfer function 0 -50 50 100 (celsius) 0.500 0.600 0.700 0.800 0.900 (volts) v temp = 0.00286(temp c ) + 0.776 for pga gain = 1 1.000 c8051f040/1/2/3/4/5/6/7 58 rev. 1.5 sfr definition 5.5. adc0cf: adc0 conf iguration register bits7-3: ad0sc4-0: adc0 sar co nversion clock period bits sar conversion clock is derived from sys tem clock by the following equation, where ad0sc refers to the 5-bit value held in ad0sc4-0, and clk sar0 refers to the desired adc0 sar clock. see table 5.2 for sar clock configuration requirements. * or *note: ad0sc is the rounded-up result. bits2-0: amp0gn2-0: adc0 internal amplifier gain (pga) 000: gain = 1 001: gain = 2 010: gain = 4 011: gain = 8 10x: gain = 16 11x: gain = 0.5 r/w r/w r/w r/w r/w r/w r/w r/w reset value ad0sc4 ad0sc3 ad0sc2 ad0sc1 ad0sc0 amp0gn2 amp0gn1 amp0gn0 11111000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: sfr page: 0xbc 0 ad 0 sc sysclk clk sar 0 -------------- -------- - 1? ? clk sar 0 sysclk ad 0 sc 1+ ---------------- ------------ = c8051f040/1/2/3/4/5/6/7 rev. 1.5 59 sfr definition 5.6. adc0cn: adc0 control bit7: ad0en: adc0 enable bit. 0: adc0 disabled. adc0 is in low-power shutdown. 1: adc0 enabled. adc0 is active and ready for data conversions. bit6: ad0tm: adc track mode bit 0: when the adc is enabled, tracking is co ntinuous unless a conversion is in process 1: tracking defined by ad0cm1-0 bits bit5: ad0int: adc0 conversion complete interrupt flag. this flag must be cleared by software. 0: adc0 has not completed a data conversion since the last time this flag was cleared. 1: adc0 has completed a data conversion. bit4: ad0busy: adc0 busy bit. read: 0: adc0 conversion is complete or a conversion is not currently in progress. ad0int is set to logic 1 on the fa lling edge of ad0busy. 1: adc0 conversion is in progress. write: 0: no effect. 1: initiates adc0 conversion if ad0cm1-0 = 00b bit3-2: ad0cm1-0: adc0 start of conversion mode select. if ad0tm = 0: 00: adc0 conversion initiated on every write of ?1? to ad0busy. 01: adc0 conversion initiated on overflow of timer 3. 10: adc0 conversion initiated on rising edge of external cnvstr0. 11: adc0 conversion initiated on overflow of timer 2. if ad0tm = 1: 00: tracking starts with the wr ite of ?1? to ad0busy and last s for 3 sar clocks, followed by conversion. 01: tracking started by the overflow of time r 3 and last for 3 sar clocks, followed by con- version. 10: adc0 tracks only when cnvstr0 input is logic low; conversion starts on rising cnvstr0 edge. 11: tracking started by the overflow of timer 2 and last for 3 sar clocks, followed by con- version. bit1: ad0wint: adc0 window compare interrupt flag. this bit must be cleared by software. 0: adc0 window comparison data match has no t occurred since this flag was last cleared. 1: adc0 window comparison data match has occurred. bit0: ad0ljst: adc0 left justify select. 0: data in adc0h:adc0l r egisters are right-justified. 1: data in adc0h:adc0l r egisters are left-justified. r/w r/w r/w r/w r/w r/w r/w r/w reset value ad0en ad0tm ad0int ad0busy ad0cm 1 ad0cm0 ad0wint ad0ljst 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 bit addressable sfr address: sfr page: 0xe8 0 c8051f040/1/2/3/4/5/6/7 60 rev. 1.5 sfr definition 5.7. adc0h: adc0 data word msb sfr definition 5.8. adc0l: adc0 data word lsb bits7-0: adc0 data word high-order bits. for ad0ljst = 0: bits 7-4 are the sign extension of bit3. bits 3-0 are the upper 4 bits of the 12-bit adc0 data word. for ad0ljst = 1: bits 7-0 are the most-significant bits of the 12-bit adc0 data word. r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: sfr address: sfr page: 0xbf 0 bits7-0: adc0 data word low-order bits. for ad0ljst = 0: bits 7-0 are the lower 8 bits of the 12-bit adc0 data word. for ad0ljst = 1: bits 7-4 are the lower 4 bits of the 12-bit adc0 data word. bits3-0 will always read ?0?. r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: sfr address: sfr page: 0xbe 0 c8051f040/1/2/3/4/5/6/7 rev. 1.5 61 figure 5.7. adc0 data word example 12-bit adc0 data word appears in the adc0 data word registers as follows: adc0h[3:0]:adc0l[7:0], if ad0ljst = 0 (adc0h[7:4] will be sign-extension of ad c0h.3 for a differential reading, otherwise = 0000b). adc0h[7:0]:adc0l[7:4], if ad0ljst = 1 (adc0l[3:0] = 0000b). example: adc0 data word conversion map, ain0 input in single-ended mode (amx0cf = 0x00, amx0sl = 0x00) example: adc0 data word conversion map, ain0-ain1 differential input pair (amx0cf = 0x01, amx0sl = 0x00) for ad0ljst = 0: ; ?n? = 12 for single-ended ; ?n?=11 for differential. ain0-agnd (volts) adc0h:adc0l (ad0ljst = 0) adc0h:adc0l (ad0ljst = 1) vref * (4095/4096) 0x0fff 0xfff0 vref / 2 0x0800 0x8000 vref * (2047/4096) 0x07ff 0x7ff0 0 0x0000 0x0000 ain0-agnd (volts) adc0h:adc0l (ad0ljst = 0) adc0h:adc0l (ad0ljst = 1) vref * (2047/2048) 0x07ff 0x7ff0 vref / 2 0x0400 0x4000 vref * (1/2048) 0x0001 0x0010 0 0x0000 0x0000 -vref * (1/2048) 0xffff (-1d) 0xfff0 -vref / 2 0xfc00 (-1024d) 0xc000 -vref 0xf800 (-2048d) 0x8000 code vin gain vref --------------- ? 2 n ? = c8051f040/1/2/3/4/5/6/7 62 rev. 1.5 5.4. adc0 programmable window detector the adc0 programmable window detector continuousl y compares the adc0 output to user-programmed limits, and notifies the system when an out-of-bound conditi on is detected. this is es pecially effective in an interrupt-driven system, saving code space and cpu bandwidth while delivering faster system response times. the window detector interrupt flag (ad0wint in adc0cn) can also be used in polled mode. the high and low bytes of the reference words are loaded into the adc0 greater-than and adc0 less-than registers (adc0gth, adc0gtl, adc0lth, and adc0 ltl). reference comparisons are shown starting on page 63. notice that the window detector flag can be asserted when the measured data is inside or out- side the user-programmed limits, depending on th e programming of the adc0gtx and adc0ltx regis- ters. sfr definition 5.9. adc0gth: adc0 greater-than data high byte sfr definition 5.10. adc0gtl: adc0 greate r-than dat a low byte sfr definition 5.11. adc0lth: adc0 less-than data high byte bits7-0: high byte of adc0 greater-than data word. r/w r/w r/w r/w r/w r/w r/w r/w reset value 11111111 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: sfr page: 0xc5 0 bits7-0: low byte of adc0 greater-than data word. r/w r/w r/w r/w r/w r/w r/w r/w reset value 11111111 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: sfr page: 0xc4 0 bits7-0: high byte of adc0 less-than data word. r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: sfr page: 0xc7 0 c8051f040/1/2/3/4/5/6/7 rev. 1.5 63 sfr definition 5.12. adc0ltl: adc0 less-than data low byte figure 5.8. 12-bit adc0 w indow in terrupt example: right justified single-ended data bits7-0: low byte of adc0 less-than data word. r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: sfr page: 0xc6 0 given: amx0sl = 0x00, amx0cf = 0x00 ad0ljst = ?0?, adc0lth:adc0ltl = 0x0200, adc0gth:adc0gtl = 0x0100. an adc0 end of conversion will cause an adc0 window compare interrupt (ad0wint = ?1?) if the resulti ng adc0 data word is < 0x0200 and > 0x0100. given: amx0sl = 0x00, amx0cf = 0x00, ad0ljst = ?0?, adc0lth:adc0ltl = 0x0100, adc0gth:adc0gtl = 0x0200. an adc0 end of conversion will cause an adc0 window compare interrupt (ad0wint = ?1?) if the resulting adc0 data word is > 0x0200 or < 0x0100. 0x0fff 0x0201 0x0200 0x01ff 0x0101 0x0100 0x00ff 0x0000 ad0wint=1 ad0wint not affected ad0wint not affected adc data word 0x0fff 0x0201 0x0200 0x01ff 0x0101 0x0100 0x00ff 0x0000 ad0wint=1 ad0wint not affected ad0wint=1 adc0lth:adc0ltl adc0gth:adc0gtl adc data word adc0gth:adc0gtl adc0lth:adc0ltl 0 input voltage (ad0 - agnd) ref x (4095/4096) ref x (256/4096) ref x (512/4096) 0 input voltage (ad0 - agnd) ref x (4095/4096) ref x (256/4096) ref x (512/4096) c8051f040/1/2/3/4/5/6/7 64 rev. 1.5 figure 5.9. 12-bit adc0 window in terrupt example: right justified differential data 0x07ff 0x0101 0x0100 0x00ff 0x0000 0xffff 0xfffe 0xf800 ad0wint=1 ad0wint not affected ad0wint not affected 0x07ff 0x0101 0x0100 0x00ff 0x0000 0xffff 0xfffe 0xf800 ad0wint=1 ad0wint not affected -ref input voltage (ad0 - ad1) ad0wint=1 ref x (2047/2048) adc0lth:adc0ltl adc0gth:adc0gtl adc data word adc data word adc0lth:adc0ltl adc0gth:adc0gtl ref x (256/2048) ref x (-1/2048) -ref input voltage (ad0 - ad1) ref x (2047/2048) ref x (256/2048) ref x (-1/2048) given: amx0sl = 0x00, amx0cf = 0x01, ad0ljst = ?0?, adc0lth:adc0ltl = 0x0100, adc0gth:adc0gtl = 0xffff. an adc0 end of conversion will cause an adc0 window compare interrupt (ad0wint = ?1?) if the resulti ng adc0 data word is < 0x0100 and > 0xffff. (in two?s-complement math, 0xffff = -1.) given: amx0sl = 0x00, amx0cf = 0x01, ad0ljst = ?0?, adc0lth:adc0ltl = 0xffff, adc0gth:adc0gtl = 0x0100. an adc0 end of conversion will cause an adc0 window compare interrupt (ad0wint = ?1?) if the resulting adc0 data word is < 0xffff or > 0x0100. (in two?s-complement math, 0xffff = -1.) c8051f040/1/2/3/4/5/6/7 rev. 1.5 65 figure 5.10. 12-bit adc0 wi ndow interrupt example: left justified single-ended data 0xfff0 0x2010 0x2000 0x1ff0 0x1010 0x1000 0x0ff0 0x0000 ad0wint=1 ad0wint not affected ad0wint not affected adc data word 0xfff0 0x2010 0x2000 0x1ff0 0x1010 0x1000 0x0ff0 0x0000 ad0wint=1 ad0wint not affected ad0wint=1 adc0lth:adc0ltl adc0gth:adc0gtl adc data word adc0gth:adc0gtl adc0lth:adc0ltl 0 input voltage (ad0 - agnd) ref x (4095/4096) ref x (256/4096) ref x (512/4096) 0 input voltage (ad0 - agnd) ref x (4095/4096) ref x (256/4096) ref x (512/4096) given: amx0sl = 0x00, amx0cf = 0x00, ad0ljst = ?1?, adc0lth:adc0ltl = 0x2000, adc0gth:adc0gtl = 0x1000. an adc0 end of conversion will cause an adc0 window compare interrupt (ad0wint = ?1?) if the resulti ng adc0 data word is < 0x2000 and > 0x1000. given: amx0sl = 0x00, amx0cf = 0x00, ad0ljst = ?1? adc0lth:adc0ltl = 0x1000, adc0gth:adc0gtl = 0x2000. an adc0 end of conversion will cause an adc0 window compare interrupt (ad0wint = ?1?) if the resulting adc0 data word is < 0x1000 or > 0x2000. c8051f040/1/2/3/4/5/6/7 66 rev. 1.5 figure 5.11. 12-bit adc0 wind ow interrupt example: left justified differential data 0x7ff0 0x1010 0x1000 0x0ff0 0x0000 0xfff0 0xffe0 0x8000 ad0wint=1 ad0wint not affected ad0wint not affected 0x7ff0 0x1010 0x1000 0x0ff0 0x0000 0xfff0 0xffe0 0x8000 ad0wint=1 ad0wint not affected -ref input voltage (ad0 - ad1) ad0wint=1 ref x (2047/2048) adc0lth:adc0ltl adc0gth:adc0gtl adc data word adc data word adc0lth:adc0ltl adc0gth:adc0gtl ref x (256/2048) ref x (-1/2048) -ref input voltage (ad0 - ad1) ref x (2047/2048) ref x (256/2048) ref x (-1/2048) given: amx0sl = 0x00, amx0cf = 0x01, ad0ljst = ?1?, adc0lth:adc0ltl = 0x1000, adc0gth:adc0gtl = 0xfff0. an adc0 end of conversion will cause an adc0 window compare interrupt (ad0wint = ?1?) if the resulti ng adc0 data word is < 0x1000 and > 0xfff0. (two?s-complement math.) given: amx0sl = 0x00, amx0cf = 0x01, ad0ljst = ?1?, adc0lth:adc0ltl = 0xfff0, adc0gth:adc0gtl = 0x1000. an adc0 end of conversion will cause an adc0 window compare interrupt (ad0wint = ?1?) if the resulting adc0 data word is < 0xfff0 or > 0x1000. (two?s-complement math.) c8051f040/1/2/3/4/5/6/7 rev. 1.5 67 table 5.2. 12-bit adc0 electrical characteristics v dd = 3.0 v, av+ = 3.0 v, vref = 2.40 v (refbe = 0), pga gain = 1, ?40 to +85 c unless otherwise specified. parameter conditions min typ max units dc accuracy resolution 12 bits integral nonlinearity ? ? 1 lsb differential nonlinearity guaranteed monotonic ? ? 1 lsb offset error note 1 ? 0.53 ? lsb full scale error differential mode; see note 1 ? 0.43 ? lsb offset temperature coefficient ? 0.25 ? ppm/c dynamic performance (10 khz sine-wave input, 0 to 1 db below full scale, 100 ksps) signal-to-noise plus distortion 66 ? ? db total harmonic distortion up to the 5 th harmonic ? ?75 ? db spurious-free dynamic range ? 80 ? db conversion rate maximum sar clock frequency ? ? 2.5 mhz conversion time in sar clocks 16 ? ? clocks track/hold acquisition time 1.5 ? ? s throughput rate ? ? 100 ksps analog inputs input voltage range single-ended operation 0 ? vref v common-mode voltage range differential operation agnd ? av+ v input capacitance ? 10 ? pf temperature sensor nonlinearity notes 1, 2 ? 1 ? c absolute accuracy notes 1, 2 ? 3 ? c gain notes 1, 2 ? 2.86 0.034 ? mv/c offset notes 1, 2 (temp = 0 c) ? 0.776 0.009 ? v power specifications power supply current (av+ sup - plied to adc) operating mode, 100 ksps ? 450 900 a power supply rejection ? 0.3 ? mv/v notes: 1. re presents one standard deviation from the mean. 2. inclu des adc offset, gain, and linearity variations. c8051f040/1/2/3/4/5/6/7 68 rev. 1.5 table 5.3. high-voltage difference amplif ier electrical characteristics v dd = 3.0 v, av+ = 3.0 v, v ref = 3.0 v, ?40 to +85 c unless otherwise specified. parameter conditions min typ max units analog inputs differential range peak-to-peak ??60 v common mode range (hvain+) ? (hvain?) = 0 v ?60 ? +60 v analog output output voltage range 0.1 ? 2.9 v dc performance common mode rejection ratio vcm= ?10 v to +10 v, rs =0 44 52 ? db offset voltage ?3? mv noise hvcap floating ?500?nv/rthz nonlinearity g = 1 ?72? db dynamic performance small signal bandwidth g = 0.05 ?3? mhz small signal bandwidth g = 1 ?150? khz slew rate ?2? v/s settling time 0.01%, g = 0.05, 10 v step ?10? s input/output impedance differential (hvain+) input ?105? k ? differential (h v ain-) input ?98? k ? common mode input ?51? k ? hvcap ?5? k ? power specification quiescent current ? 450 1000 a c8051f040/1/2/3/4/5/6/7 rev. 1.5 69 6. 10-bit adc (adc0, c8051f042/3/4/5/6/7 only) the adc0 subsystem for the c8051f 042/3/4/5/6/7 consists of a 9-channel, configurable analog multi- plexer (amux0), a programmable gain amplifier (pga 0), and a 100 ksps, 10-bit successive-approxima- tion-register adc with integrated track-and-hold an d programmable window detector (see block diagram in figure 6.1). the amux0, pga0, data conversion modes, and window detector are all configurable under software control via the special function registers shown in figure 6.1. the voltage reference used by adc0 is selected as described in section ?9. voltage reference (c8051f040/2/4/6)? on page 113 for c8051f042/4/6 devices, or section ?10. voltage reference (c8051f041/3/5/7)? on page 117 for c8051f043/5/7 devices. the adc0 subsystem (adc0, track-and-hold and pga0) is enabled only when the ad0en bit in the adc0 control register (adc0cn) is set to logic 1. the adc0 subsystem is in low power shutdown when this bit is logic 0. figure 6.1. 10-bit adc0 functional block diagram 6.1. analog multiplexer and pga the analog multiplexer can input analog signals to th e adc from four external analog input pins, port 3 port pins (optionally configured as analog input pins), high voltage difference amplifier, and an internally connected on-chip temperature sensor (temperature tr ansfer function is shown in figure 6.6). amux input pairs can be programmed to operate in either differential or single-ended mode. this allows the user to select the best measurement technique for each in put channel, and even accommodates mode changes "on-the-fly". the amux defaults to all single-ended inputs upon reset. there are three registers associated with the amux: the channel selection register amx0sl (sfr definition 6.2), th e configuration register amx0cf (sfr definition 6.1), and the port pin selection register amx0pr t (sfr definition 6.3). table 6.1 shows amux functionality by channel for ea ch possible configuratio n. the pga amplifies the amux output signal by an amount determined by the states of the amp0gn2-0 bi ts in the adc0 configu- ration register, adc0cf (sfr definition 6.5). the pga can be software-programmed for gains of 0.5, 2, 4, 8 or 16. gain defaults to unity on reset. 10-bit sar adc ref + - av+ temp sensor 10 9-to-1 amux (se or diff) av+ 20 10 ad0en sysclk x start conversion agnd amx0cf adc0l adc0h adc0ltl adc0lth adc0gtl adc0gth amx0sl amx0ad0 amx0ad1 amx0ad2 amx0ad3 ain01ic ain23ic hvda2ic port3ic adc0cf amp0gn0 amp0gn1 amp0gn2 ad0sc0 ad0sc1 ad0sc2 ad0sc3 ad0sc4 adc0cn ad0ljst ad0wint ad0cm0 ad0cm1 ad0busy ad0int ad0tm ad0en timer 3 overflow 00 01 10 11 ad0busy (w) cnvstr0 ad0wint comb. logic hv input port 3 i/o pins analog input pins agnd timer 2 overflow c8051f040/1/2/3/4/5/6/7 70 rev. 1.5 6.1.1. analog input configuration the analog multiplexer routes signal s from external analog input pins, port 3 i/o pins (programmed to be analog inputs), a high voltage difference amplifier, and an on-chip temperature sensor as shown in figure 6.2. figure 6.2. analog input diagram analog signals may be input from four external analog input pins (ain0.0 through ain0.3) as differential or single-ended measurements. additionally, port 3 i/o po rt pins may be configured to input analog signals. port 3 pins configured as analog inputs are selected using the port pin selection register (amx0prt). any number of port 3 pins may be selected simultaneously as inputs to the amux. even numbered port 3 pins and odd numbered port 3 pins are routed to separate amux inputs. ( note: even port pins and odd port pins that are simultaneously selected will be shorted toge ther as ?wired-or?.) in this way, differential mea- surements may be made when using the port 3 pins (voltage difference between selected even and odd port 3 pins) as shown in figure 6.2. the high-voltage difference amplifier (hvda) will accept analog input sign als and reject up to 60 volts common-mode for differential measurement of up to the reference voltage to the adc (0 to vref volts). the output of the hvda can be selected as an input to the adc using the amux as any other channel is selected for measurement. + - + - + - 9-to-1 amux (se or diff) amx0cf ain01ic ain23ic hvdaic port3ic 10-bit sar adc x temp sensor agnd ain0.0 ain0.1 ain0.2 ain0.3 amx0sl amx0ad0 amx0ad1 amx0ad2 amx0ad3 0 7 6 5 4 3 2 1 8 hv amp hvcap hvref hvain - hvain + p3.6 p3.4 p3.2 p3.0 p3.7 p3.5 p3.3 p3.1 (wired-or) (wired-or) amx0prt pain0en pain2en pain4en pain6en pain7en pain5en pain3en pain1en p3even p3odd + - c8051f040/1/2/3/4/5/6/7 rev. 1.5 71 sfr definition 6.1. amx0cf: amux0 configuration sfr definition 6.2. amx0sl: amux0 channel select bits7-4: unused. read = 0000b; write = don?t care bit3: port3ic: port 3 even/odd pin input pair configuration bit 0: port 3 even and odd input channels are independent single-ended inputs 1: port 3 even and odd input channels are (respectively) +, - differential input pair bit2: hvda2c: hvda 2?s compliment bit 0: hvda output measured as an independent single-ended input 1: 2?s compliment va lue result from hvda bit1: ain23ic: ain2, ain3 in put pair configuration bit 0: ain2 and ain3 are independent single-ended inputs 1: ain2, ain3 are (respectively ) +, - differential input pair bit0: ain01ic: ain0, ain1 in put pair configuration bit 0: ain0 and ain1 are independent single-ended inputs 1: ain0, ain1 are (respectively ) +, - differential input pair note: the adc0 data word is in 2?s complement format for channels configured as differential. r r r r r/w r/w r/w r/w reset value - - - - port3ic hvda2c ain23ic ain01ic 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: sfr address: sfr page: 0xba 0 bits7-4: unused. read = 0000b; write = don?t care bits3-0: amx0ad3-0: amx0 address bits 0000-1111b: adc inputs selected per table 6.1. r r r r r/w r/w r/w r/w reset value - - - - amx0ad3 amx0ad2 amx0ad1 amx0ad0 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: sfr page: 0xbb 0 c8051f040/1/2/3/4/5/6/7 72 rev. 1.5 note: ?p3even? denotes even numbered and ?p3odd? odd numbered port 3 pins selected in the amx0prt register. table 6.1. amux selection chart (amx0ad3-0 and amx0cf3-0 bits) amx0ad3-0 0000 0001 0010 0011 0100 0101 0110 0111 1xxx amx0cf bits 3-0 0000 ain0.0 ain0.1 ain0.2 ain0.3 hvda agnd p3even p3odd temp senso r 0001 +(ain0.0) -(ain0.1) ain0.2 ain0.3 hvda agnd p3even p3odd temp senso r 0010 ain0.0 ain0.1 +(ain0.2) -(ain0.3) hvda agnd p3even p3odd temp senso r 0011 +(ain0.0) -(ain0.1) +(ain0.2) -(ain0.3) hvda agnd p3even p3odd temp senso r 0100 ain0.0 ain0.1 ain0.2 ain0.3 +(hvda) -(hvref) p3even p3odd temp senso r 0101 +(ain0.0) -(ain0.1) ain0.2 ain0.3 +(hvda) -(hvref) p3even p3odd temp senso r 0110 ain0.0 ain0.1 +(ain0.2) -(ain0.3) +(hvda) -(hvref) p3even p3odd temp senso r 0111 +(ain0.0) -(ain0.1) +(ain0.2) -(ain0.3) +(hvda) -(hvref) p3even p3odd temp senso r 1000 ain0.0 ain0.1 ain0.2 ain0.3 hvda agnd +p3even -p3odd temp senso r 1001 +(ain0.0) -(ain0.1) ain0.2 ain0.3 hvda agnd +p3even -p3odd temp senso r 1010 ain0.0 ain0.1 +(ain0.2) -(ain0.3) hvda agnd +p3even -p3odd temp senso r 1011 +(ain0.0) -(ain0.1) +(ain0.2) -(ain0.3) hvda agnd +p3even -p3odd temp senso r 1100 ain0.0 ain0.1 ain0.2 ain0.3 +(hvda) -(hvref) +p3even -p3odd) temp senso r 1101 +(ain0.0) -(ain0.1) ain0.2 ain0.3 +(hvda) -(hvref) +p3even -p3odd temp senso r 1110 ain0.0 ain0.1 +(ain0.2) -(ain0.3) +(hvda) -(hvref) +p3even -p3odd temp senso r 1111 +(ain0.0) -(ain0.1) +(ain0.2) -(ain0.3) +(hvda) -(hvref) +p3even -p3odd temp senso r c8051f040/1/2/3/4/5/6/7 rev. 1.5 73 sfr definition 6.3. amx0prt: port 3 pin selection bit7: pain7en: pin 7 analog input enable bit 0: p3.7 is not selected as an analog input to the amux. 1: p3.7 is selected as an analog input to the amux. bit6: pain6en: pin 6 analog input enable bit 0: p3.6 is not selected as an analog input to the amux. 1: p3.6 is selected as an analog input to the amux. bit5: pain5en: pin 5 analog input enable bit 0: p3.5 is not selected as an analog input to the amux. 1: p3.5 is selected as an analog input to the amux. bit4: pain4en: pin 4 analog input enable bit 0: p3.4 is not selected as an analog input to the amux. 1: p3.4 is selected as an analog input to the amux. bit3: pain3en: pin 3 analog input enable bit 0: p3.3 is not selected as an analog input to the amux. 1: p3.3 is enabled as an analog input to the amux. bit2: pain2en: pin 2 analog input enable bit 0: p3.2 is not selected as an analog input to the amux. 1: p3.2 is enabled as an analog input to the amux. bit1: pain1en: pin 1 analog input enable bit 0: p3.1 is not selected as an analog input to the amux. 1: p3.1 is enabled as an analog input to the amux. bit0: pain0en: pin 0 analog input enable bit 0: p3.0 is not selected as an analog input to the amux. 1: p3.0 is enabled as an analog input to the amux. note: any number of port 3 pins may be selected simultaneously inputs to the amux. odd num- bered and even numbered pins that are select ed simultaneously are shorted together as ?wired-or?. r/w r/w r/w r/w r/w r/w r/w r/w reset value pain7en pain6en pain5en pain4en pain3en pain2en pain1en pain0en 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: sfr page: 0xba 0 c8051f040/1/2/3/4/5/6/7 74 rev. 1.5 6.2. high-voltage difference amplifier the high-voltage difference amplifier (hvda) can be used to measure high differential voltages up to 60 v peak-to-peak, reject high common-mode voltages up to 60 v, and condition the signal voltage range to be suitable for input to adc0. the input signal to the hvda may be below agnd to ?60 volts, and as high as +60 volts, making the device suitable for both single and dual supply applications. the hvda pro- vides a common-mode signal for the adc via the hi gh voltage reference input (hvref), allowing mea- surement of signals outside the specified adc input r ange using on-chip circuitry. the hvda has a gain of 0.05 v/v to 14 v/v. the first stage 20:1 difference amplifier has a gain of 0.05 v/v when the output ampli- fier is used as a unity gain buffer. when the output am plifier is set to a gain of 280 (selected using the hvgain bits in the high voltage control register), an overall gain of 14 can be attained. the hvda uses four available external pins: +hva in, ?hvain, hvcap, and hvref. hvain+ and hvain- serve as the differential inputs to the hvda. hvref should be used to provide a common mode reference for input to adc0, and to prevent the output of the hvda circuit from saturating. th e output from the hvda circuit as calculated by equation 6.1 must re main within the ?output voltage range? specification listed in table 6.3. the ideal value for hvref in most applications is equal to 1/2 the supply voltage for the device. when the adc is configured for differential measurement, the hvref signal is applied to the ain- input of the adc, thereby removing hvref from the measurement. hvcap facilitates the use of a capac- itor for noise filtering in conjuncti on with r7 (see figure 6.3 for r7 and other approximate resistor values). alternatively, the hvcap could also be used to access amplification of the first stage of the hvda at an external pin. (see table 6.3 on page 90 fo r electrical specifications of the hvda.) equation 6.1. calculating hvda output voltage to ain+ figure 6.3. high voltage differen ce amplifier functional diagram v out hvain + ?? hvain - ?? ? ?? gain hvref + ? = note: the output voltage of the hvda is selected as an input to the ain+ input of adc0 via its analog multiplexer (amux0). hvda output voltages outside the adc?s input ra nge will result in saturation of the adc input. allow for adequate settle/tracking time for proper voltage measurements. ??? k ? 5k ? 100k ? 5k ? hva0cn gain setting hvain- hvain+ hvref hvcap vout (to amux0) 5k ? c8051f040/1/2/3/4/5/6/7 rev. 1.5 75 sfr definition 6.4. hva0cn: high voltage differ ence amplifier control bit7: hvdaen: high voltage difference amplifier (hvda) enable bit. 0: the hvda is disabled. 1: the hvda is enabled. bits6-3: reserved. bits2-0: hvgain3-hvgain0: hvda gain control bits. hvda gain control bits set the amplification gain if the difference signal input to the hvda as defined in the table below: r/w r r r r/w r/w r/w r/w reset value hvdaen - - - hvgain3 hvgain 2 hvgain1 hvgain0 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: sfr page: 0xd6 0 hvgain3:hvgain0 hvda gain 0000 0.05 0001 0.1 0010 0.125 0011 0.2 0100 0.25 0101 0.4 0110 0.5 0111 0.8 1000 1.0 1001 1.6 1010 2.0 1011 3.2 1100 4.0 1101 6.2 1110 7.6 1111 14 c8051f040/1/2/3/4/5/6/7 76 rev. 1.5 6.3. adc modes of operation adc0 has a maximum conver sion speed of 100 ksps. the adc0 conversion clock is derived from the sys- tem clock divided by the va lue held in the adc0sc bits of register adc0cf. 6.3.1. starting a conversion a conversion can be initiated in one of four ways, depending on the programmed states of the adc0 start of conversion mode bits (ad0cm1, ad0cm0) in ad c0cn. conversions may be initiated by the following: ? writing a ?1? to the ad0busy bit of adc0cn; ? a timer 3 overflow (i.e., ti me d continuous conversions); ? a rising edge detected on the external adc convert start signal, cnvstr0; ? a timer 2 overflow (i.e., ti me d continuous conversions). the ad0busy bit is set to logic 1 during conversion and re stored to logic 0 when conversion is complete. the falling edge of ad0busy triggers an interrupt (when en abled) and sets the ad 0int interrupt flag (adc0cn.5). converted data is available in the adc0 data word msb and lsb r egisters, adc0 h, adc0l. converted data can be either left or right justifie d in the adc0h:adc0l register pair (see example in figure 6.7) depending on the programmed state of the ad0ljst bit in the adc0cn register. when initiating conversions by writ ing a ?1? to ad0busy, the ad0int bit should be polled to determine when a conversion has completed (adc0 interrupts may also be us ed). the recommen ded polling proce- dure is shown below. step 1. write a ?0? to ad0int; step 2. write a ?1? to ad0busy; step 3. poll ad0int for ?1?; step 4. process adc0 data. 6.3.2. tracking modes according to table 6.2, each adc0 conversion must be preceded by a minimum tracking time for the con- verted result to be accurate. the ad0tm bit in register adc0cn controls the adc0 track-and-hold mode. in its default state, the adc0 input is continuously tracked when a conversion is not in progress. when the ad0tm bit is logic 1, adc0 operat es in low-power tracking mode. in this mode, each conversion is pre- ceded by a tracking period of 3 sar clocks after th e start-of-conversion signal. when the cnvstr0 signal is used to initiate conversions in low-power tracking mode, adc0 tra cks only when cnvstr0 is low; con- version begins on the rising edge of cnvstr0 (see figure 6.4). tracking can also be disabled when the entire chip is in low power standby or sleep mode s. low-power tracking mode is also useful when amux or pga settings are frequently changed, to ensure that settling time requirements are met (see section ?6.3.3. settling time requirements? on page 78 ). c8051f040/1/2/3/4/5/6/7 rev. 1.5 77 figure 6.4. 10-bit adc track and conversion example timing 123456789 1 0 1 1 1 2 1 3 1 4 1 5 1 6 cnvstr (ad0cm[1:0]=10) adc0tm=1 adc0tm=0 timer 2, timer 3 overflow; write '1' to ad0busy (ad0cm[1:0]=00, 01, 11) adc0tm=1 adc0tm=0 a. adc timing for external trigger source b. adc timing for internal trigger sources sar clocks sar clocks 123456789 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 123456789 1 0 1 1 1 2 1 3 1 4 1 5 1 6 sar clocks track convert low power mode low power or convert track or convert convert track track convert low power mode low power or convert track or convert convert track c8051f040/1/2/3/4/5/6/7 78 rev. 1.5 6.3.3. settling time requirements a minimum tracking time is required before an accurate conversion can be performe d. this tracking time is determined by the adc0 mux resistance, the adc0 sampling capacitance, any external source resis- tance, and the accuracy required fo r the conversion. figure 6.5 shows th e equivalent adc0 input circuits for both differential and single-ended modes. notice that the equivalent time constant for both input cir- cuits is the same. the required settlin g time for a given settling accuracy ( sa ) may be approximated by equation 6.2. when measuring the temperature sensor output, r total reduces to r mux . note that in low- power tracking mode, three sar clocks are used for tracking at the start of every conversion. for most applications, these th ree sar clocks will meet the tracking requ irements. see table 6.2 for absolute mini- mum settling/tracking time requirements. equation 6.2. adc0 settling time requirements where: sa is the settling accuracy, given as a fraction of an lsb (for example, 0.25 to settle within 1/4 lsb) t is the r equired settling time in seconds r total is the sum of the adc0 mux resistanc e and any external source resistance. n is the ad c resolution in bits (10). figure 6.5. adc0 eq uivalent input circuits t 2 n sa ------ - ?? ?? r total c sample ? r mux = 5k rc input = r mux * c sample r mux = 5k c sample = 10pf c sample = 10pf mux select mux select differential mode ain0.x ain0.y r mux = 5k c sample = 10pf rc input = r mux * c sample mux select single-ended mode ain0.x c8051f040/1/2/3/4/5/6/7 rev. 1.5 79 figure 6.6. temperature sensor transfer function 0 -50 50 100 (celsius) 0.500 0.600 0.700 0.800 0.900 (volts) v temp = 0.00286(temp c ) + 0.776 for pga gain = 1 1.000 c8051f040/1/2/3/4/5/6/7 80 rev. 1.5 sfr definition 6.5. adc0cf: adc0 configuration bits7-3: ad0sc4-0: adc0 sar co nversion clock period bits sar conversion clock is derived from sys tem clock by the following equation, where ad0sc refers to the 5-bit value held in ad0sc4-0, and clk sar0 refers to the desired adc0 sar clock. see table 6.2 on page 89 for sar clock setting requirements. * or *note: ad0sc is the rounded-up result. bits2-0: amp0gn2-0: adc0 internal amplifier gain (pga) 000: gain = 1 001: gain = 2 010: gain = 4 011: gain = 8 10x: gain = 16 11x: gain = 0.5 r/w r/w r/w r/w r/w r/w r/w r/w reset value ad0sc4 ad0sc3 ad0sc2 ad0sc1 ad0sc0 amp0gn2 amp0gn1 amp0gn0 11111000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: sfr page: 0xbc 0 ad 0 sc sysclk clk sar 0 -------------- -------- - 1? ? clk sar 0 sysclk ad 0 sc 1+ --------------- ------------- = c8051f040/1/2/3/4/5/6/7 rev. 1.5 81 sfr definition 6.6. adc0cn: adc0 control bit7: ad0en: adc0 enable bit. 0: adc0 disabled. adc0 is in low-power shutdown. 1: adc0 enabled. adc0 is active and ready for data conversions. bit6: ad0tm: adc track mode bit 0: when the adc is enabled, tracking is co ntinuous unless a conversion is in process 1: tracking defined by ad0cm1-0 bits bit5: ad0int: adc0 conversion complete interrupt flag. this flag must be cleared by software. 0: adc0 has not completed a data conversion since the last time this flag was cleared. 1: adc0 has completed a data conversion. bit4: ad0busy: adc0 busy bit. read: 0: adc0 conversion is complete or a conversion is not currently in progress. ad0int is set to logic 1 on the fa lling edge of ad0busy. 1: adc0 conversion is in progress. write: 0: no effect. 1: initiates adc0 conversion if ad0cm1-0 = 00b bit3-2: ad0cm1-0: adc0 start of conversion mode select. if ad0tm = 0: 00: adc0 conversion initiated on every write of ?1? to ad0busy. 01: adc0 conversion initiated on overflow of timer 3. 10: adc0 conversion initiated on rising edge of external cnvstr0. 11: adc0 conversion initiated on overflow of timer 2. if ad0tm = 1: 00: tracking starts with the wr ite of ?1? to ad0busy and last s for 3 sar clocks, followed by conversion. 01: tracking started by the overflow of time r 3 and last for 3 sar clocks, followed by con- version. 10: adc0 tracks only when cnvstr0 input is logic low; conversion starts on rising cnvstr0 edge. 11: tracking started by the overflow of timer 2 and last for 3 sar clocks, followed by con- version. bit1: ad0wint: adc0 window compare interrupt flag. this bit must be cleared by software. 0: adc0 window comparison data match has no t occurred since this flag was last cleared. 1: adc0 window comparison data match has occurred. bit0: ad0ljst: adc0 left justify select. 0: data in adc0h:adc0l r egisters are right-justified. 1: data in adc0h:adc0l r egisters are left-justified. r/w r/w r/w r/w r/w r/w r/w r/w reset value ad0en ad0tm ad0int ad0busy ad0cm1 ad0cm0 ad0wint ad0ljst 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 bit addressable sfr address: sfr page: 0xe8 0 c8051f040/1/2/3/4/5/6/7 82 rev. 1.5 sfr definition 6.7. adc0h: adc0 data word msb sfr definition 6.8. adc0l: adc0 data word lsb bits7-0: adc0 data word high-order bits. for ad0ljst = 0: bits 7-2 are the sign extension of bit 1. bits 0 and 1 are the upper 2 bits of the 10-bit adc0 data word. for ad0ljst = 1: bits 7-0 are the most-significant bits of the 10-bit adc0 data word. r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: sfr address: sfr page: 0xbf 0 bits7-0: adc0 data word low-order bits. for ad0ljst = 0: bits 7-0 are the lower 8 bits of the 10-bit adc0 data word. for ad0ljst = 1: bits 6 and 7 are the lower 2 bits of the 10-bit adc0 data word. bits 5-0 r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: sfr address: sfr page: 0xbe 0 c8051f040/1/2/3/4/5/6/7 rev. 1.5 83 figure 6.7. adc0 data word example 10-bit adc data word appears in the adc data word registers as follows: adc0h[1:0]:adc0l[7:0], if adljst = 0 (adc0h[7:2] will be sign-extension of ad c0h.1 for a differential reading, otherwise = 000000b). adc0h[7:0]:adc0l[7:6], if adljst = 1 (adc0l[5:0] = 000000b). example: adc data word conversion map, ain0 input in single-ended mode (amx0cf = 0x00, amx0sl = 0x00) example: adc data word conversion map, ain0-ain1 differential input pair (amx0cf = 0x01, amx0sl = 0x00) adljst = 0: ; ?n? = 10 for single-end ed; ?n?=9 for differential. ain0-agnd (volts) adc0h:adc0l (adljst = 0) adc0h:adc0l (adljst = 1) vref * (1023/1024) 0x03ff 0xffc0 vref / 2 0x0200 0x8000 vref * (511/1024) 0x01ff 0x7fc0 0 0x0000 0x0000 ain0-agnd (volts) adc0h:adc0l (adljst = 0) adc0h:adc0l (adljst = 1) vref * (511/512) 0x01ff 0x7fc0 vref / 2 0x0100 0x4000 vref * (1/512) 0x0001 0x0040 0 0x0000 0x0000 -vref * (1/512) 0xffff (-1) 0xffc0 -vref / 2 0xff00 (-256) 0xc000 -vref 0xfe00 (-512) 0x8000 code vin gain vref --------------- ? 2 n ? = c8051f040/1/2/3/4/5/6/7 84 rev. 1.5 6.4. adc0 programmable window detector the adc0 programmable window detector continuousl y compares the adc0 output to user-programmed limits, and notifies the system when an out-of-bound conditi on is detected. this is es pecially effective in an interrupt-driven system, saving code space and cpu bandwidth while delivering faster system response times. the window detector interrupt flag (ad0wint in adc0cn) can also be used in polled mode. the high and low bytes of the reference words are loaded into the adc0 greater-than and adc0 less-than registers (adc0gth, adc0gtl, adc0lth, and adc0 ltl). reference comparisons are shown starting on page 85. notice that the window detector flag can be asserted when the measured data is inside or out- side the user-programmed limits, depending on th e programming of the adc0gtx and adc0ltx regis- ters. sfr definition 6.9. adc0gth: adc0 greater-than data high byte sfr definition 6.10. adc0gtl: adc0 greate r-than dat a low byte sfr definition 6.11. adc0lth: adc0 less-than data high byte bits7-0: high byte of adc0 greater-than data word. r/w r/w r/w r/w r/w r/w r/w r/w reset value 11111111 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: sfr page: 0xc5 0 bits7-0: low byte of adc0 greater-than data word. r/w r/w r/w r/w r/w r/w r/w r/w reset value 11111111 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: sfr page: 0xc4 0 bits7-0: high byte of adc0 less-than data word. r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: sfr page: 0xc7 0 c8051f040/1/2/3/4/5/6/7 rev. 1.5 85 sfr definition 6.12. adc0ltl: adc0 less-than data low byte figure 6.8. 10-bit adc0 w indow in terrupt example: right justified single-ended data bits7-0: low byte of adc0 less-than data word. r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: sfr page: 0xc6 0 given: amx0sl = 0x00, amx0cf = 0x00, adljst = 0, adc0lth:adc0ltl = 0x0200, adc0gth:adc0gtl = 0x0100. an adc end of conversion will cause an adc window compare interrupt (adwint=1) if the resulting adc data word is < 0x0200 and > 0x0100. given: amx0sl = 0x00, amx0cf = 0x00, adljst = 0, adc0lth:adc0ltl = 0x0100, adc0gth:adc0gtl = 0x0200. an adc end of conversion will cause an adc window compare interrupt (adwint=1) if the resulting adc data word is > 0x0200 or < 0x0100. 0x03ff 0x0201 0x0200 0x01ff 0x0101 0x0100 0x00ff 0x0000 ad0wint=1 ad0wint not affected ad0wint not affected adc data word 0x03ff 0x0201 0x0200 0x01ff 0x0101 0x0100 0x00ff 0x0000 ad0wint=1 ad0wint not affected ad0wint=1 adc0lth:adc0ltl adc0gth:adc0gtl adc data word adc0gth:adc0gtl adc0lth:adc0ltl 0 input voltage (ad0 - agnd) ref x (1023/1024) ref x (256/1024) ref x (512/1024) 0 input voltage (ad0 - agnd) ref x (1023/1024) ref x (256/1024) ref x (512/1024) c8051f040/1/2/3/4/5/6/7 86 rev. 1.5 figure 6.9. 10-bit adc0 window in terrupt example: right justified differential data given: amx0sl = 0x00, amx0cf = 0x01, adljst = 0, adc0lth:adc0ltl = 0x0100, adc0gth:adc0gtl = 0xffff. an adc end of conversion will cause an adc window compare interrupt (adwint=1) if the resulting adc data word is < 0x0100 and > 0xffff. (in two?s-complement math, 0xffff = -1.) given: amx0sl = 0x00, amx0cf = 0x01, adljst = 0, adc0lth:adc0ltl = 0xffff, adc0gth:adc0gtl = 0x0100. an adc end of conversion will cause an adc window compare interrupt (adwint=1) if the resulting adc data word is < 0xffff or > 0x0100. (in two?s-complement math, 0xffff = -1.) 0x01ff 0x0101 0x0100 0x00ff 0x0000 0xffff 0xfffe 0xfe00 ad0wint=1 ad0wint not affected ad0wint not affected 0x01ff 0x0101 0x0100 0x00ff 0x0000 0xffff 0xfffe 0xfe00 ad0wint=1 ad0wint not affected -ref input voltage (ad0 - ad1) ad0wint=1 ref x (511/512) adc0lth:adc0ltl adc0gth:adc0gtl adc data word adc data word adc0lth:adc0ltl adc0gth:adc0gtl ref x (256/512) ref x (-1/512) -ref input voltage (ad0 - ad1) ref x (511/512) ref x (256/512) ref x (-1/512) c8051f040/1/2/3/4/5/6/7 rev. 1.5 87 figure 6.10. 10-bit adc0 wi ndow interrupt example: left justified single-ended data given: amx0sl = 0x00, amx0cf = 0x00, adljst = 1, adc0lth:adc0ltl = 0x8000, adc0gth:adc0gtl = 0x4000. an adc end of conversion will cause an adc window compare interrupt (adwint=1) if the resulting adc data word is < 0x8000 and > 0x4000. given: amx0sl = 0x00, amx0cf = 0x00, adljst = 1, adc0lth:adc0ltl = 0x4000, adc0gth:adc0gtl = 0x8000. an adc end of conversion will cause an adc window compare interrupt (adwint=1) if the resulting adc data word is < 0x4000 or > 0x8000. 0xffc0 0x8040 0x8000 0x7fc0 0x4040 0x4000 0x3fc0 0x0000 ad0wint=1 ad0wint not affected ad0wint not affected adc data word 0xffc0 0x8040 0x8000 0x7fc0 0x4040 0x4000 0x3fc0 0x0000 ad0wint=1 ad0wint not affected ad0wint=1 adc0lth:adc0ltl adc0gth:adc0gtl adc data word adc0gth:adc0gtl adc0lth:adc0ltl 0 input voltage (ad0 - agnd) ref x (1023/1024) ref x (256/1024) ref x (512/1024) 0 input voltage (ad0 - agnd) ref x (1023/1024) ref x (256/1024) ref x (512/1024) c8051f040/1/2/3/4/5/6/7 88 rev. 1.5 figure 6.11. 10-bit adc0 wind ow interrupt example: left justified differential data given: amx0sl = 0x00, amx0cf = 0x01, adljst = 1, adc0lth:adc0ltl = 0x4000, adc0gth:adc0gtl = 0xffc0. an adc end of conversi on will cause an adc window compare interrupt (adwint=1) if the resulting adc data word is < 0x4000 and > 0xffc0. (two?s-complement math.) given: amx0sl = 0x00, amx0cf = 0x01, adljst = 1, adc0lth:adc0ltl = 0xffc0, adc0gth:adc0gtl = 0x4000. an adc end of conversi on will cause an adc window compare interrupt (adwint=1) if the resulting adc data word is < 0xffc0 or > 0x4000. (two?s-complement math.) 0x7fc0 0x4040 0x4000 0x3fc0 0x0000 0xffc0 0xff80 0x8000 ad0wint=1 ad0wint not affected ad0wint not affected 0x7fc0 0x4040 0x4000 0x3fc0 0x0000 0xffc0 0xff80 0x8000 ad0wint=1 ad0wint not affected -ref input voltage (ad0 - ad1) ad0wint=1 ref x (511/512) adc0lth:adc0ltl adc0gth:adc0gtl adc data word adc data word adc0lth:adc0ltl adc0gth:adc0gtl ref x (256/512) ref x (-1/512) -ref input voltage (ad0 - ad1) ref x (511/512) ref x (256/512) ref x (-1/512) c8051f040/1/2/3/4/5/6/7 rev. 1.5 89 table 6.2. 10-bit adc0 electrical characteristics v dd = 3.0 v, av+ = 3.0 v, v ref = 2.40 v (refbe = 0), pga gain = 1, ?40 to +85 c unless otherwise specified. parameter conditions min typ max units dc accuracy resolution 10 bits integral nonlinearity ??1 lsb differential nonlinearity guaranteed monotonic ??1 lsb offset error ?0.21? lsb full scale error differential mode ?0.11? lsb offset temperature coefficient ? 0.25 ? ppm/c dynamic performance (10 khz sine-wave input, 0 to 1 db below full scale, 100 ksps) signal-to-noise plus distortion 59 ? ? db total harmonic distortion up to the 5 th harmonic ??70? db spurious-free dynamic range ?80? db conversion rate sar clock frequency ??2.5mhz conversion time in sar clocks 16 ? ? clocks track/hold acquisition time 1.5 ? ? s throughput rate ??100ksps analog inputs input voltage range single-ended operation 0 ? vref v common-mode voltage range differential operation agnd ? av+ v input capacitance ?10? pf temperature sensor nonlinearity 1,2 ?1? c absolute accuracy 1,2 ?3? c gain 1,2 ?2.86 0.034 ?mv/c offset 1,2 te m p = 0 c ?0.776 0.009 ?v power specifications power supply current (av+ supplied to adc) operating mode, 100 ksps ?450900 a power supply rejection ?0.3? mv/v notes: 1. re presents one standard deviation from the mean. 2. inclu des adc offset, gain, and linearity variations. c8051f040/1/2/3/4/5/6/7 90 rev. 1.5 table 6.3. high-voltage difference amplif ier electrical characteristics v dd = 3.0 v, av+ = 3.0 v, v ref = 3.0 v, ?40 to +85 c unless otherwise specified. parameter conditions min typ max units analog inputs differential range peak-to-peak ??60 v common mode range (hvain+) ? (hvain?) = 0 v ?60 ? +60 v analog output output voltage range 0.1 ? 2.9 v dc performance common mode rejection ratio vcm= ?10 v to +10 v, rs =0 44 52 ? db offset voltage ?3? mv noise hvcap floating ?500?nv/rthz nonlinearity g = 1 ?72? db dynamic performance small signal bandwidth g = 0.05 ?3?mhz small signal bandwidth g = 1 ?150? khz slew rate ?2?v/s settling time 0.01%, g = 0.05, 10 v step ?10? s input/output impedance differential (hvain+) input ?105? k ? differential (h v ain?) input ?98? k ? common mode input ?51? k ? hvcap ?5?k ? power specification quiescent current ? 450 1000 a c8051f040/1/2/3/4/5/6/7 rev. 1.5 91 7. 8-bit adc (adc2, c8051f040/1/2/3 only) the adc2 subsystem for the c8051f040/1/2/3 consists of an 8-channel, configurable analog multiplexer, a programmable gain amplifier, and a 500 ksps, 8-bi t successive-approximation -register adc with inte- grated track-and-hold (see block diagram in figure 7.1). the amux2, pga2, and data conversion modes, are all configurable under software control via the special function registers shown in figure 7.1. the adc2 subsystem (8-bit adc, track- and-hold and pga) is enabled only when the ad2en bit in the adc2 control register (adc2cn) is set to logic 1. the adc2 subsystem is in low power shutdown when this bit is logic 0. the voltage reference used by adc2 is selected as described in section ?9. voltage reference (c8051f040/2/4/6)? on page 113 for c8051f040/2 devices, or section ?10. voltage reference (c8051f041/3/5/7)? on page 117 for c8051f041/3 devices. figure 7.1. adc2 functional block diagram 7.1. analog multiplexer and pga eight adc2 channels are available for measurement, as selected by the amx2sl register (see sfr defi- nition 7.2). the pga amplifies the adc2 output sig nal by an amount determin ed by the states of the amp2gn2-0 bits in the adc2 configuration register, adc2cf (sfr definition 7.1). the pga can be soft- ware-programmed for gains of 0.5, 1, 2, or 4. gain defaults to 0.5 on reset. important note : ain2 pins also function as port 1 i/o pins, and must be configured as analog inputs when used as adc2 inputs. to configure an ain2 pin for analog input, set to ?0? the corresponding bit in register p1mdin. port 1 pins selected as analog inpu ts are skipped by the digital i/o crossbar. see section ?17.1.5. configuring port 1, 2, and 3 pins as analog inputs? on page 207 for more information on con- figuring the ain2 pins. 8-bit sar adc ref + - av+ 8 av+ ad2en sysclk x agnd adc2 adc2cf amp2gn0 amp2gn1 ad2sc0 ad2sc1 ad2sc2 ad2sc3 ad2sc4 amx2sl adc2cn ad2cm0 ad2cm1 ad2cm2 ad2busy ad2int ad2tm ad2en start conversion timer 3 overflow timer 2 overflow 000 001 010 011 write to ad2busy cnvstr 1xx write to ad0busy (synchronized with adc0) amx2ad0 amx2ad1 amx2ad2 8-to-1 amux ain2.0 (p1.0) ain2.1 (p1.1) ain2.2 (p1.2) ain2.3 (p1.3) ain2.4 (p1.4) ain2.5 (p1.5) ain2.6 (p1.6) ain2.7 (p1.7) + - + - + - + - amx2cf ain01ic ain23ic ain45ic ain67ic adc2lth adc2gth 16 dig comp adc window interrupt c8051f040/1/2/3/4/5/6/7 92 rev. 1.5 7.2. adc2 modes of operation adc2 has a maximum conversion speed of 500 ksps . the adc2 conversion clock (sar2 clock) is a divided version of the system clock, determined by the ad2sc bits in the adc2cf register (system clock divided by (ad2sc + 1) for 0 ? ad2sc ?? 31). the maximum adc2 conversion clock is 7.5 mhz. 7.2.1. starting a conversion a conversion can be initiated in one of five ways, dep ending on the programmed states of the adc2 start of conversion mode bits (ad2cm2?0) in adc2cn. conversions may be initiated by the following: ?writing a ?1? to the ad2busy bit of adc2cn; ?a timer 3 overflow (i.e., timed continuous conversions); ?a rising edge detected on the external adc c onver t start signal, cnvstr2 or cnvstr0 (see important note below); ?a timer 2 overflow (i.e., timed continuous conversions); ?writing a ?1? to the ad0busy of register adc0 cn (initiate conv ersion of adc2 and adc0 with a single software command). ? an important note about external convert start (cnvstr0 and cnvstr2) : if cnvstr2 is enabled in the digital crossbar ( section ?17.1. ports 0 through 3 and the priority crossbar decoder? on page 204 ), cnvstr2 will be the external convert start signal for adc2. however, if only cnvstr0 is enabled in the digital crossbar and cnvstr2 is not enabled, then cnvstr0 may serve as the start of conversion for both adc0 and adc2. this permits synchronous sampling of both adc0 and adc2. during conversion, the ad2busy bit is set to logic 1 and restored to 0 when conversion is complete. the falling edge of ad2busy trigge rs an interrupt (when enab led) and sets the interr upt flag in adc2cn. con- verted data is available in the adc2 data word, adc2. when a conversion is initiated by wr iting a ?1? to ad2busy, it is reco mmended to poll ad2int to determine when the conversion is complete. the recommended procedure is: step 1. write a ?0? to ad2int; step 2. write a ?1? to ad2busy; step 3. poll ad2int for ?1?; step 4. process adc2 data. 7.2.2. tracking modes according to table 7.2, each adc2 conversion must be preceded by a minimum tracking time for the con- verted result to be accurate. the ad2tm bit in register adc2cn controls the adc2 track-and-hold mode. in its default state, the adc2 input is continuously tr acked, except when a conversion is in progress. when the ad2tm bit is logic 1, adc2 operates in low-power tracking mode. in this mode, each conversion is pre- ceded by a tracking period of 3 sar clocks (after the start-of-conversion signal). when the cnvstr2 (or cnvstr0, see section 7.2.1 above) signal is used to initiate conversions in low-power tracking mode, adc2 tracks only when cnvstr2 is low; conversi on begins on the rising edge of cnvstr2 (see figure 7.2). tracking can also be disabled (shutdown) when the entire chip is in low power standby or sleep modes. low-power track-and-hold mode is also useful when amux or pga settings are frequently changed, due to the settling time requirements described in section ?7.2.3. settling time require- ments? on page 94 . c8051f040/1/2/3/4/5/6/7 rev. 1.5 93 figure 7.2. adc2 track a nd conversion example timing write '1' to ad2busy, timer 3 overflow, timer 2 overflow, write '1' to ad0busy (ad2cm[2:0]=000, 001, 011, 0xx) ad2tm=1 ad2tm=0 sar2 clocks 123456789101112 123456789 sar2 clocks track convert low power mode low power or convert track or convert convert track b. adc timing for internal trigger source 123456789 cnvstr2/cnvstr0 (ad2cm[2:0]=010) ad2tm=1 a. adc timing for external trigger source sar2 clocks track or convert convert track ad2tm=0 track convert low power mode low power or convert c8051f040/1/2/3/4/5/6/7 94 rev. 1.5 7.2.3. settling time requirements a minimum tracking time is required before an accurate conversion can be performe d. this tracking time is determined by the adc2 mux resistance, the adc2 sampling capacitance, any external source resis- tance, and the accuracy required for the conversion. fi gure 7.3 shows the equivalent adc2 input circuit. the required adc2 settling time for a given settling a ccuracy (sa) may be approximated by equation 7.1. note: an absolute minimum settling time of 0.8 s required after any mux select ion. note that in low- power tracking mode, three sar2 clocks are used for tracking at the start of every conversion. for most applications, these three sar2 clocks will meet the tracking requirements. equation 7.1. adc2 settling time requirements where: sa is the settling accuracy, given as a fraction of an lsb (for example, 0.25 to settle within 1/4 lsb) t is the r equired settling time in seconds r total is the sum of the adc2 mux resistanc e and any external source resistance. n is the ad c resolution in bits (8). figure 7.3. adc2 e quivalent input circuit t 2 n sa ------ - ?? ?? r total c sample ? r mux = 5k c sample = 10pf rc input = r mux * c sample mux select ain2.x c8051f040/1/2/3/4/5/6/7 rev. 1.5 95 sfr definition 7.1. amx2cf: amux2 configuration sfr definition 7.2. amx2sl: amux2 channel select bits7-4: unused. read = 0000b; write = don?t care bit3: pin67ic: p1.6, p1.7 i nput pair configuration bit 0: p1.6 and p1.7 are independent single-ended inputs 1: p1.6, p1.7 are (respectively) +, - differential input pair bit2: pin45ic: p1.4, p1.5 i nput pair configuration bit 0: p1.4 and p1.5 are independent single-ended inputs 1: p1.4, p1.5 are (respectively) +, - differential input pair bit1: pin23ic: p1.2, p1.3 i nput pair configuration bit 0: p1.2 and p1.3 are independent single-ended inputs 1: p1.2, p1.3 are (respectively) +, - differential input pair bit0: pin01ic: p1.0, p1.1 i nput pair configuration bit 0: p1.0 and p1.1 are independent single-ended inputs 1: p1.0, p1.1 are (respectively) +, - differential input pair note: the adc2 data word is in 2?s complement format for channels configured as differential. rrrrr / wr / wr / wr / wr e s e t v a l u e - - - - pin67ic pin45ic pin23ic pin01ic 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: sfr page: 0xba 2 bits7-3: unused. read = 00000b; write = don?t care bits2-0: amx2ad2-0: amx2 address bits 000-111b: adc inputs selected per table 7.1. rrrrrr / wr / wr / wr e s e t v a l u e - - - - - amx2ad2 amx2ad1 amx2ad0 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: sfr page: 0xbb 2 c8051f040/1/2/3/4/5/6/7 96 rev. 1.5 table 7.1. amux selection chart (amx2 ad2-0 and amx2cf3 -0 bits) amx2ad2-0 000 001 010 011 100 101 110 111 amx2cf bits 3-0 0000 p1.0 p1.1 p1.2 p1.3 p1.4 p1.5 p1.6 p1.7 0001 +(p1.0) -(p1.1) -(p1.0) +(p1.1) p1.2 p1.3 p1.4 p1.5 p1.6 p1.7 0010 p1.0 p1.1 +(p1.2) -(p1.3) -(p1.2) +(p1.3) p1.4 p1.5 p1.6 p1.7 0011 +(p1.0) -(p1.1) -(p1.0) +(p1.1) +(p1.2) -(p1.3) -(p1.2) +(p1.3) p1.4 p1.5 p1.6 p1.7 0100 p1.0 p1.1 p1.2 p1.3 +(p1.4) -(p1.5) -(p1.4) +(p1.5) p1.6 p1.7 0101 +(p1.0) -(p1.1) -(p1.0) +(p1.1) p1.2 p1.3 +(p1.4) -(p1.5) -(p1.4) +(p1.5) p1.6 p1.7 0110 p1.0 p1.1 +(p1.2) -(p1.3) -(p1.2) +(p1.3) +(p1.4) -(p1.5) -(p1.4) +(p1.5) p1.6 p1.7 0111 +(p1.0) -(p1.1) -(p1.0) +(p1.1) +(p1.2) -(p1.3) -(p1.2) +(p1.3) +(p1.4) -(p1.5) -(p1.4) +(p1.5) p1.6 p1.7 1000 p1.0 p1.1 p1.2 p1.3 p1.4 p1.5 +(p1.6) -(p1.7) -(p1.6) +(p1.7) 1001 +(p1.0) -(p1.1) -(p1.0) +(p1.1) p1.2 p1.3 p1.4 p1.5 +(p1.6) -(p1.7) -(p1.6) +(p1.7) 1010 p1.0 p1.1 +(p1.2) -(p1.3) -(p1.2) +(p1.3) p1.4 p1.5 +(p1.6) -(p1.7) -(p1.6) +(p1.7) 1011 +(p1.0) -(p1.1) -(p1.0) +(p1.1) +(p1.2) -(p1.3) -(p1.2) +(p1.3) p1.4 p1.5 +(p1.6) -(p1.7) -(p1.6) +(p1.7) 1100 p1.0 p1.1 p1.2 p1.3 +(p1.4) -(p1.5) -(p1.4) +(p1.5) +(p1.6) -(p1.7) -(p1.6) +(p1.7) 1101 +(p1.0) -(p1.1) -(p1.0) +(p1.1) p1.2 p1.3 +(p1.4) -(p1.5) -(p1.4) +(p1.5) +(p1.6) -(p1.7) -(p1.6) +(p1.7) 1110 p1.0 p1.1 +(p1.2) -(p1.3) -(p1.2) +(p1.3) +(p1.4) -(p1.5) -(p1.4) +(p1.5) +(p1.6) -(p1.7) -(p1.6) +(p1.7) 1111 +(p1.0) -(p1.1) -(p1.0) +(p1.1) +(p1.2) -(p1.3) -(p1.2) +(p1.3) +(p1.4) -(p1.5) -(p1.4) +(p1.5) +(p1.6) -(p1.7) -(p1.6) +(p1.7) c8051f040/1/2/3/4/5/6/7 rev. 1.5 97 sfr definition 7.3. adc2cf: adc2 configuration bits7-3: ad2sc4-0: adc2 sar co nversion clock period bits sar conversion clock is derived from sys tem clock by the following equation, where ad2sc refers to the 5-bit value held in ad2sc4-0. sar conversion clock requirements are given in table 7.2. * or *note: ad2sc is the rounded-up result. bit2: unused. read = 0b . write = don?t care. bits1-0: amp2gn1-0: adc2 internal amplifier gain (pga) 00: gain = 0.5 01: gain = 1 10: gain = 2 11: gain = 4 r/w r/w r/w r/w r/w r r/w r/w reset value ad2sc4 ad2sc3 ad2sc2 ad2sc1 ad2sc0 - amp2gn1 amp2gn0 11111000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: sfr page: 0xbc 2 ad 2 sc sysclk clk sar 2 -------------- -------- - 1? ? clk sar 2 sysclk ad 2 sc 1+ --------------- ------------- ? = c8051f040/1/2/3/4/5/6/7 98 rev. 1.5 sfr definition 7.4. adc2cn: adc2 control bit7: ad2en: adc2 enable bit. 0: adc2 disabled. adc2 is in low-power shutdown. 1: adc2 enabled. adc2 is active and ready for data conversions. bit6: ad2tm: adc2 track mode bit. 0: normal track mode: when adc2 is enabled, tracki ng is continuous unless a conversion is in process. 1: low-power track mode: tracking def ined by ad2cm2-0 bits (see below). bit5: ad2int: adc2 conversion complete interrupt flag. this flag must be cleared by software. 0: adc2 has not completed a data conversion since the last time this flag was cleared. 1: adc2 has completed a data conversion. bit4: ad2busy: adc2 busy bit. read: 0: adc2 conversion is complete or a conversion is not currently in progress. ad2int is set to logic 1 on the falling edge of ad2busy. 1: adc2 conversion is in progress. write: 0: no effect. 1: initiates adc2 conversion if ad2cm2-0 = 000b bits3-1: ad2cm2-0: adc2 start of conversion mode select. ad2tm = 0: 000: adc2 conversion initiated on every write of ?1? to ad2busy. 001: adc2 conversion initiated on overflow of timer 3. 010: adc2 conversion initiated on rising edge of external cnvstr2 or cnvstr0. 011: adc2 conversion initiated on overflow of timer 2. 1xx: adc2 conversion initiated on write of ?1? to ad0busy (synchronized with adc0 software- commanded conversions). ad2tm = 1: 000: tracking initiated on write of ?1? to ad2busy and lasts 3 sar2 clocks, followed by conver- sion. 001: tracking initiated on overflow of timer 3 and lasts 3 sar2 clocks, followed by conversion. 010: adc2 tracks only when cnvstr2 (or cnvstr0, see section 7.2.1) input is logic low; con- version starts on rising cnvstr2 edge. 011: tracking initiated on overflow of timer 2 and lasts 3 sar2 clocks, followed by conversion. 1xx: tracking initiated on write of ?1? to ad0busy and lasts 3 sar2 clocks, followed by conver- sion. bit0: ad2wint: adc2 window compare interrupt flag. 0: adc2 window comparison data match has not occurred since this flag was last cleared. 1: adc2 window comparison data match has occurred. this flag must be cleared in software. an important note about external co nvert start (cnvstr0 and cnvstr2) : if cnvstr2 is enabled in the digital crossbar ( section ?17.1. ports 0 through 3 and the priority crossbar decoder? on page 204 ), cnvstr2 will be the external convert start signal for adc2. however, if only cnvstr0 is enabled in the digital crossbar and cnvstr2 is not enabl ed, then cnvstr0 may serve as the start of conversion for both adc0 and adc2. r/w r/w r/w r/w r/w r/w r/w r/w reset value ad2en ad2tm ad2int ad2busy ad2cm2 ad2cm1 ad2cm0 ad2wint 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: sfr page: 0xe8 2 c8051f040/1/2/3/4/5/6/7 rev. 1.5 99 sfr definition 7.5. adc2: adc2 data word figure 7.4. adc2 data word example bits7-0: adc2 data word. r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: sfr page: 0xbe 2 8-bit adc data word appears in the adc2 data word register as follows: example: adc2 data word conversion map, ain1.0 input (amx2sl = 0x00) ain1.0-agnd (volts) adc2 vref * (255/256) 0xff vref / 2 0x80 vref * (127/256) 0x7f 0 0x00 code vin gain vref --------------- ? 256 ? = c8051f040/1/2/3/4/5/6/7 100 rev. 1.5 7.3. adc2 programmable window detector the adc2 programmable window detector continuousl y compares the adc2 output to user-programmed limits, and notifies the system when an out-of-bound conditi on is detected. this is es pecially effective in an interrupt-driven system, saving code space and cpu bandwidth while delivering faster system response times. the window detector interrupt flag (ad2wint in adc2cn) can also be used in polled mode. the reference words are loaded into the adc2 greater-than and adc2 less-than registers (adc2gt and adc2lt). notice that the window detector flag can be asserted when the measured data is inside or out- side the user-programmed limits, depending on the programming of the adc2gt and adc2lt registers. sfr definition 7.6. adc2gt: adc2 greater-than data sfr definition 7.7. adc2lt: adc2 less-than data 7.3.1. window detector in single-ended mode figure 7.5 shows two example window comparisons for single-ended mode, with adc2lt = 0x20 and adc2gt = 0x10. in single-ended mode, the codes vary from 0 to vref x (255/256) and are represented as 8-bit unsigned integers. in the left example, an ad2wint interrupt will be generated if the adc2 con- version word (adc2) is within the range defined by adc2gt and adc2lt (if 0x10 ? adc2 ? 0x20). in the right example, and ad2wint interr upt will be generated if adc2 is outside of the range defined by adc2gt and adc2lt (if adc2 ? 0x10 or adc2 ? 0x20). bits7-0: high byte of adc2 greater-than data word. r/w r/w r/w r/w r/w r/w r/w r/w reset value 11111111 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: sfr page: 0xc4 2 bits7-0: low byte of adc2 greater-than data word. r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: sfr page: 0xc6 2 c8051f040/1/2/3/4/5/6/7 rev. 1.5 101 figure 7.5. adc window compare examples , single-ended mode 0xff 0x21 0x20 0x1f 0x11 0x10 0x0f 0x00 0 input voltage (p1.x - gnd) ref x (255/256) ref x (32/256) ref x (16/256) ad2wint=1 ad2wint not affected ad2wint not affected adc2lt adc2gt 0xff 0x21 0x20 0x1f 0x11 0x10 0x0f 0x00 0 input voltage (p1.x - gnd) ref x (255/256) ref x (32/256) ref x (16/256) ad2wint not affected adc2gt adc2lt ad2wint=1 ad2wint=1 adc2 adc2 c8051f040/1/2/3/4/5/6/7 102 rev. 1.5 7.3.2. window detector in differential mode figure 7.6 shows two example window comparisons for differential mode, with adc2lt = 0x10 (+16d) and adc2gt = 0xff (?1d). notice that in differential mode, the codes vary from ?vref to vref x (127/128) and are represented as 8-bit 2s complement signed integers. in the left example, an ad2wint interrupt will be generated if the adc2 conv ersion word (adc2l) is within th e range defined by adc2gt and adc2lt (if 0xff (?1d) < adc2 < 0x0f (16d)). in th e right example, an ad2wint interrupt will be gener- ated if adc2 is outside of the range defined by ad c2gt and adc2lt (if adc2 < 0xff (?1d) or adc2 > 0x10 (+16d)). figure 7.6. adc window comp are examples, di fferential mode 0x7f (127d) 0x11 (17d) 0x10 (16d) 0x0f (15d) 0x00 (0d) 0xff (-1d) 0xfe (-2d) 0x80 (-128d) -ref input voltage (p1.x - p1.y) ref x (127/128) ref x (16/128) ref x (-1/256) 0x7f (127d) 0x11 (17d) 0x10 (16d) 0x0f (15d) 0x00 (0d) 0xff (-1d) 0xfe (-2d) 0x80 (-128d) -ref input voltage (p1.x - p1.y) ref x (127/128) ref x (16/128) ref x (-1/256) ad2wint=1 ad2wint not affected ad2wint not affected adc2lt adc2gt ad2wint not affected adc2gt adc2lt ad2wint=1 ad2wint=1 adc2 adc2 c8051f040/1/2/3/4/5/6/7 rev. 1.5 103 table 7.2. adc2 electrical characteristics v dd = 3.0 v, av+ = 3.0 v, v ref2 = 2.40 v (refbe = 0), pga2 = 1, ?40 to +85 c unless otherwise specified. parameter conditions min typ max units dc accuracy resolution 8b i t s integral nonlinearity ??1lsb differential nonlinearity guaranteed monotonic ??1lsb offset error ? 0.50.3 ? lsb full scale error differential mode ? ?10.2 ? lsb dynamic performance (10 khz sine-wave input, 0 to 1 db below full scale, 500 ksps) signal-to-noise plus distortion 45 47 ? db total harmonic distortion up to the 5 th harmonic ??51? db spurious-free dynamic range ?52? db conversion rate sar conversion clock ? frequency ?? 6 mhz conversion time in sar clocks 8 ? ? clocks track/hold acquisition time 300 ? ? ns throughput rate ??500ksps analog inputs input voltage range single-ended 0 ? vref v common mode range 0?av+v input capacitance ?5? pf power specifications power supply current (av+ supplied to adc2) operating mode, 500 ksps ?420900 a power supply rejection ?0.3? mv/v c8051f040/1/2/3/4/5/6/7 104 rev. 1.5 c8051f040/1/2/3/4/5/6/7 rev. 1.5 105 8. dacs, 12-bit voltage mo de (c8051f040/1/2/3 only) each c8051f040/1/2/3 devices include two on-chip 12 -bit voltage-mode digital-to-analog converters (dacs). each dac has an output swing of 0 v to (vre f ? 1 lsb) for a corresponding input code range of 0x000 to 0xfff. the dacs may be enabled/disabled via their corresponding control registers, dac0cn and dac1cn. while disabled, the dac output is maintained in a high-impedance state, and the dac sup- ply current falls to 1 a or less. the voltage reference for each dac is supplied at the vrefd pin (c8051f040/2 devices) or the vref pin (c8051f041/3 devices). note that the vref pin on c8051f041/3 devices may be driven by the internal voltage reference or an external source. if the internal voltage refer- ence is used it must be enabled in order for the dac outputs to be valid. see section ?9. voltage refer- ence (c8051f040/2/4 /6)? on page 113 or section ?10. voltage reference (c8051f041/3/5/7)? on page 117 for more information on configuring the voltage reference for the dacs. figure 8.1. dac functi onal block diagram dac0 av+ 12 agnd 8 8 ref dac0 dac0cn dac0en dac0md1 dac0md0 dac0df2 dac0df1 dac0df0 dac0h dac0l dig. mux latch latch 8 8 dac1 av+ 12 agnd 8 8 ref dac1 dac1cn dac1en dac1md1 dac1md0 dac1df2 dac1df1 dac1df0 dac1h dac1l dig. mux latch latch 8 8 dac0h timer 3 timer 4 timer 2 dac1h timer 3 timer 4 timer 2 c8051f040/1/2/3/4/5/6/7 106 rev. 1.5 8.1. dac output scheduling each dac features a flexible output update mechan ism which allows for seam less full-scale changes and supports jitter-free update s for waveform generation. the following ex amples are written in terms of dac0, but dac1 operation is identical. 8.1.1. update output on-demand in its default mode (dac0cn.[4:3] = ?00?) the dac0 output is updated ?on-demand? on a write to the high- byte of the dac0 data register (dac0h). it is importan t to note that writes to dac0l are held, and have no effect on the dac0 output until a wr ite to dac0h takes place. if writi ng a full 12-bit word to the dac data registers, the 12-bit data word is written to the low byte (dac0l) and high by te (dac0h) data registers. data is latched into dac0 after a writ e to the corresponding dac0h register, so the write sequence should be dac0l followed by dac0h if the full 12-bit resolution is required. the dac can be used in 8- bit mode by initializing dac0l to th e desired value (typically 0x00), a nd writing data to only dac0h (also see section 8.2 for information on formatting the 12-bit dac data word wit hin the 16-bit sfr space). 8.1.2. update output based on timer overflow similar to the adc operation, in which an adc conv ersion can be initiated by a timer overflow indepen- dently of the processor, the dac outputs can use a timer overflow to schedule an output update event. this feature is useful in systems where the dac is us ed to generate a waveform of a defined sampling rate by eliminating the effects of variable interrupt latenc y and instruction execution on the timing of the dac output. when the dac0md bits (dac0cn.[4:3]) are set to ?01?, ?10?, or ?11?, writes to both dac data regis- ters (dac0l and dac0h) are held until an associated timer overflow event (timer 3, timer 4, or timer 2, respectively) occurs, at which time the dac0h:dac0l contents are copied to the dac input latches allow- ing the dac output to change to the new value. 8.2. dac output scaling/justification in some instances, input data should be shifted prio r to a dac0 write operatio n to properly justify data within the dac input registers. this action would typi cally require one or more load and shift operations, adding software overhead and slowing dac throughput. to alleviate this problem, the data-formatting fea- ture provides a means for the user to program the orie ntation of the dac0 data word within data registers dac0h and dac0l. the three dac0df bits (dac0cn.[2:0]) allow the user to specify one of five data word orientations as shown in the dac0cn register definition. dac1 is functionally the same as dac0 described above. the electrical specifications for both dac0 and dac1 are given in table 8.1. c8051f040/1/2/3/4/5/6/7 rev. 1.5 107 sfr definition 8.1. dac0h: dac0 high byte sfr definition 8.2. dac0l: dac0 low byte bits7-0: dac0 data word most significant byte. r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: sfr page: 0xd3 0 bits7-0: dac0 data word least significant byte. r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: sfr page: 0xd2 0 c8051f040/1/2/3/4/5/6/7 108 rev. 1.5 sfr definition 8.3. dac0cn: dac0 control bit7: dac0en: dac0 enable bit. 0: dac0 disabled. dac0 output pin is disa bled; dac0 is in low- power shutdown mode. 1: dac0 enabled. dac0 output pin is active; dac0 is operational. bits6-5: unused. read = 00b; write = don?t care. bits4-3: dac0md1-0: dac0 mode bits. 00: dac output updates o ccur on a write to dac0h. 01: dac output updates occur on timer 3 overflow. 10: dac output updates occur on timer 4 overflow. 11: dac output updates occur on timer 2 overflow. bits2-0: dac0df2-0: dac0 data format bits: 000: the most significant nibble of the dac0 data word is in dac0 h[3:0], while the least significant byte is in dac0l. 001: the most significant 5-bits of the dac0 data word is in dac0 h[4:0], while the least significant 7-bits are in dac0l[7:1]. 010: the most significant 6-bits of the dac0 data word is in dac0 h[5:0], while the least significant 6-bits are in dac0l[7:2]. 011: the most significant 7-bits of the dac0 data word is in dac0 h[6:0], while the least significant 5-bits are in dac0l[7:3]. 1xx: the most significant 8-bits of the dac0 data word is in dac0 h[7:0], while the least significant 4-bits are in dac0l[7:4]. r/w r r r/w r/w r/w r/w r/w reset value dac0en - - dac0md1 dac0md0 dac0df2 dac0df1 dac0df0 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: sfr page: 0xd4 0 dac0h dac0l msb lsb dac0h dac0l msb lsb dac0h dac0l msb lsb dac0h dac0l msb lsb dac0h dac0l msb lsb c8051f040/1/2/3/4/5/6/7 rev. 1.5 109 sfr definition 8.4. dac1h: dac1 high byte sfr definition 8.5. dac1l: dac1 low byte bits7-0: dac1 data word most significant byte. r/wr/wr/wr/wr/wr/wr/w r/wreset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: sfr page: 0xd3 1 bits7-0: dac1 data word least significant byte. r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: sfr page: 0xd2 1 c8051f040/1/2/3/4/5/6/7 110 rev. 1.5 sfr definition 8.6. dac1cn: dac1 control bit7: dac1en: dac1 enable bit. 0: dac1 disabled. dac1 output pin is disa bled; dac1 is in low- power shutdown mode. 1: dac1 enabled. dac1 output pin is active; dac1 is operational. bits6-5: unused. read = 00b; write = don?t care. bits4-3: dac1md1-0: dac1 mode bits: 00: dac output updates o ccur on a write to dac1h. 01: dac output updates occur on timer 3 overflow. 10: dac output updates occur on timer 4 overflow. 11: dac output updates occur on timer 2 overflow. bits2-0: dac1df2: dac1 data format bits: 000: the most significant nibble of the dac1 data word is in dac1 h[3:0], while the least significant byte is in dac1l. 001: the most significant 5-bits of the dac1 data word is in dac1 h[4:0], while the least significant 7-bits are in dac1l[7:1]. 010: the most significant 6-bits of the dac1 data word is in dac1 h[5:0], while the least significant 6-bits are in dac1l[7:2]. 011: the most significant 7-bits of the dac1 data word is in dac1 h[6:0], while the least significant 5-bits are in dac1l[7:3]. 1xx: the most significant 8-bits of the dac1 data word is in dac1 h[7:0], while the least significant 4-bits are in dac1l[7:4]. r/w r/w r/w r/w r/w r/w r/w r/w reset value dac1en - - dac1md1 dac1md0 dac1 df2 dac1df1 dac1df0 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: sfr page: 0xd4 1 dac1h dac1l msb lsb dac1h dac1l msb lsb dac1h dac1l msb lsb dac1h dac1l msb lsb dac1h dac1l msb lsb c8051f040/1/2/3/4/5/6/7 rev. 1.5 111 . table 8.1. dac electrical characteristics v dd = 3.0 v, av+ = 3.0 v, v ref = 2.40 v (refbe = 0), no output load unless otherwise specified. parameter conditions min typ max units static performance resolution 12 bits integral nonlinearity ?2? lsb differential nonlinearity ? 1l s b output noise no output filter 100 khz output filter 10 khz output filter ? ? ? 25 0 128 41 ? ? ? vrms offset error data word = 0x014 ?330 mv offset tempco ? 6 ? ppm/c full-scale error ?2060 mv full-scale error tempco ? 10 ? ppm/c v dd power supply rejection ratio ??60? db output impedance in shutdown mod e dacnen = 0 ?100? k ? output sink current ?300? a output short-circuit current data word = 0xfff ?15? ma dynamic performance voltage output slew rate load = 40 pf ?0.44? v/s output settling time to 1/2 lsb load = 40 pf, output swing from co de 0xfff to 0x014 ?10? s output voltage swing 0?vref ? lsb v startup time ?10? s analog outputs load regulation i l = 0.01 ma to 0.3 ma at code 0xfff ?60? ppm power consumption (each dac) power supply current (av+ supplied to dac) data word = 0x7ff ?110400 a c8051f040/1/2/3/4/5/6/7 112 rev. 1.5 c8051f040/1/2/3/4/5/6/7 rev. 1.5 113 9. voltage reference ( c8051f040/2/4/6 ) the voltage reference circuit offers full flexibility in operating the a dc and dac modules. three voltage ref- erence input pins allow each adc and the two dacs (c8051f040/2 only) to reference an external voltage reference or the on-chip voltage reference output. adc0 may also reference the dac0 output internally, and adc2 may reference the analog power supply voltage, via the vref multiplexers shown in figure 9.1. the internal voltage reference circuit consists of a 1.2 v, temperature stable bandgap voltage reference generator and a gain-of-two output buffer amplifier. the internal reference may be routed via the vref pin to external system components or to the voltage refe rence input pins shown in figure 9.1. bypass capaci- tors of 0.1 f and 4.7 f are recommended from the vref pin to agnd, as shown in figure 9.1. see table 9.1 for voltage reference specifications. the reference control register, ref0cn (defined in sfr definition 9.1) enables/disables the internal ref- erence generator and selects the reference inputs for adc0 and adc2. the biase bi t in ref0cn enables the on-board reference generator while the refbe bit enables the gain-of-two buffer amplifier which drives the vref pin. when disabled, the supply current drawn by the bandgap and buffer amplifier falls to less than 1 a (typical) and the output of the buffer amplifier enters a high impedance state. if the internal band- gap is used as the reference voltage generator, biase and refbe must both be set to logic 1. if the inter- nal reference is not used, refbe may be set to logic 0. note that the biase bit must be set to logic 1 if either dac or adc is used, regardless of the voltage reference used. if neither the adc nor the dac are being used, both of these bits can be set to logic 0 to conserve power. bits ad0vrs and ad2vrs select the adc0 and adc2 voltage reference sources, respectively. the electrical specifications for the voltage reference are given in table 9.1. the temperature sensor connects to the highest order input of the adc0 input multiplexer (see section ?5.1. analog multiplexer and pga? on page 47 for c8051f040 devices, or section ?6.1. analog multi- plexer and pga? on page 69 for c8051f042/4/6 devices). the tempe bit within ref0cn enables and disables the temperature sensor. while disabled, the temperature sensor defaults to a high impedance state and any a/d measurements performed on the sensor while disabled result in meaningless data. figure 9.1. voltage refere nce functional block diagram recommended bypass capacitors x2 vref dac0 dac1 ref vrefd av+ adc2 adc0 vref2 ref ref 1 0 0 1 vref0 4.7 ? f0.1 ? f ref0cn refbe biase tempe ad2vrs ad0vrs refbe biase bias to adcs, dacs 1.2v band-gap en external voltage reference circuit r1 vdd (c8051f040/2 only) (c8051f040/2 only) c8051f040/1/2/3/4/5/6/7 114 rev. 1.5 sfr definition 9.1. ref0cn: reference control bits7-5: unused. read = 000b; write = don?t care. bit4: ad0vrs: adc0 voltage reference select 0: adc0 voltage reference from vref0 pin. 1: adc0 voltage reference from dac0 output (c8051f040/2 only). bit3: ad2vrs: adc2 voltage refer ence select (c8051f040/2 only). 0: adc2 voltage reference from vref2 pin. 1: adc2 voltage reference from av+. bit2: tempe: temperature sensor enable bit. 0: internal temperature sensor off. 1: internal temperature sensor on. bit1: biase: adc/dac bias gener ator enable bit. (must be ?1? if using adc or dac). 0: internal bias generator off. 1: internal bias generator on. bit0: refbe: internal refe rence buffer enable bit. 0: internal reference buffer off. 1: internal reference buffer on. internal voltage reference is driven on the vref pin. r/w r/w r/w r/w r/w r/w r/w r/w reset value - - - ad0vrs ad2vrs tempe biase refbe 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: sfr page: 0xd1 0 c8051f040/1/2/3/4/5/6/7 rev. 1.5 115 table 9.1. voltage reference electrical characteristics v dd = 3.0 v, av+ = 3.0 v, ?40 to +85c unless otherwise specified. parameter conditions min typ max units internal reference (refbe = 1) output voltage 25 c ambient 2.36 2.43 2.48 v vref short-circuit current ?? 30 ma vref temperature coefficient ? 15 ? ppm/c load regulation load = 0 to 200 a to agnd ? 0.5 ? ppm/a vref turn-on time 1 4.7 f tantalum, 0.1 f ceramic byp ass ?2 ? ms vref turn-on time 2 0.1 f ceramic bypass ?20 ? s vref turn-on time 3 no bypass cap ?10 ? s reference buff er power sup - ply current ?40 ? a power supply rejection ? 140 ? ppm/v external reference (refbe = 0) input voltage range 1.00 ? (av+) ? 0.3 v input current ?0 1 a c8051f040/1/2/3/4/5/6/7 116 rev. 1.5 c8051f040/1/2/3/4/5/6/7 rev. 1.5 117 10. voltage referen ce (c8051f041/3/5/7) the internal voltage reference circuit consists of a 1.2 v, temperature stable bandgap voltage reference generator and a gain-of-two output buffer amplifier. the internal reference may be routed via the vref pin to external system components or to the vrefa input pin shown in figure 10.1. bypass capacitors of 0.1 f and 4.7 f are recommended from the vref pin to agnd, as shown in figure 10.1. see table 10.1 for voltage reference specifications. the vrefa pin provides a voltage reference input for adc0 and adc2 (c8051f041/3 only). adc0 may also reference the dac0 output internally (c8051f041 /3 only), and adc2 may reference the analog power supply voltage, via the vref mult iplexers shown in figure 10.1. the reference control register, ref0cn (defined in sfr definition 10.1) enables/disables the internal reference generator and selects the reference inputs for ad c0 and adc2 . the biase bit in ref0cn enables the on-board reference generator while the refbe bit enables the gain-of-two buffer amplifier which drives the vref pin. when disabled, the supply current drawn by the bandgap and buffer amplifier falls to less than 1 a (typical) and the output of the buffer amplifier enters a high impedance state. if the internal bandgap is used as the referenc e voltage generator, biase and refbe must both be set to 1 (this includes any time a dac is used). if the internal reference is not used, refbe may be set to logic 0. note that the biase bit must be set to logic 1 if either a dc is used, regardless of the voltage reference used. if neither the adc nor the dac are being used, both of these bits can be set to logic 0 to conserve power. bits ad0vrs and ad2vrs select the adc0 and adc2 voltage reference sources, respectively. the elec- trical specifications for the voltage reference are given in table 10.1. the temperature sensor connects to the highest order input of the adc0 input multiplexer (see section ?5.1. analog multiplexer and pga? on page 47 for c8051f041 devices that feature a 12-bit adc, or section ? 6.1. analog multiplexer and pga ? on page 69 for c8051f043/5/7 device s that feature a 10-bit adc). the tempe bit within ref0cn enables and disables the temperature sensor. while disabled, the temperature sensor defaults to a high impedance st ate and any a/d measurements performed on the sen- sor while disabled result in meaningless data. figure 10.1. voltage reference functional block diagram recommended bypass capacitors x2 vref dac0 dac1 ref av+ adc2 adc0 ref ref 1 0 0 1 vrefa 4.7 ? f0.1 ? f ref0cn refbe biase tempe ad2vrs ad0vrs refbe biase bias to adcs, dacs 1.2v band-gap en external voltage reference circuit r1 vdd (c8051f041/3 only) (c8051f041/3 only) c8051f040/1/2/3/4/5/6/7 118 rev. 1.5 sfr definition 10.1. ref0cn: reference control bits7-5: unused. read = 000b; write = don?t care. bit4: ad0vrs: adc0 vo ltage reference select 0: adc0 voltage reference from vrefa pin. 1: adc0 voltage reference from dac0 output (c8051f041/3 only). bit3: ad2vrs: adc2 voltage reference select (c8051f041/3 only). 0: adc2 voltage reference from vrefa pin. 1: adc2 voltage reference from av+. bit2: tempe: temperature sensor enable bit. 0: internal temperature sensor off. 1: internal temperature sensor on. bit1: biase: adc/dac bias ge nerator enable bit. (must be ?1 ? if using adc or dac). 0: internal bias generator off. 1: internal bias generator on. bit0: refbe: internal refe rence buffer enable bit. 0: internal reference buffer off. 1: internal reference buffer on. internal voltage reference is driven on the vref pin. r/w r/w r/w r/w r/w r/w r/w r/w reset value - - - ad0vrs ad1vrs tempe biase refbe 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: sfr page: 0xd1 0 c8051f040/1/2/3/4/5/6/7 rev. 1.5 119 table 10.1. voltage reference elect rical characteristics v dd = 3.0 v, av+ = 3.0 v, ?40 to +85 c unless otherwise specified. parameter conditions min typ max units internal reference (refbe = 1) output voltage 25 c ambient 2.36 2.43 2.48 v vref short-circuit current ?? 30 ma vref temperature coefficient ? 15 ? ppm/c load regulation load = 0 to 200 a to agnd ? 0.5 ? ppm/a vref turn-on time 1 4.7 f tantalum, 0.1 f ceramic byp ass ?2 ? ms vref turn-on time 2 0.1 f ceramic bypass ?20 ? s vref turn-on time 3 no bypass cap ?10 ? s reference buff er power sup - ply current ?40 ? a power supply rejection ? 140 ? ppm/v external reference (refbe = 0) input voltage range 1.00 ? (av+) ? 0.3 v input current ?0 1 a c8051f040/1/2/3/4/5/6/7 120 rev. 1.5 c8051f040/1/2/3/4/5/6/7 rev. 1.5 121 11. comparators c8051f04x family of devices include three on-chip programmable voltage comparators, shown in figure 11.1. each comparator offers programmable response time and hysteresis. when assigned to a port pin, the comparator output may be configured as open drain or push-pull, and comparator inputs should be configured as analog inputs (see section ?17.1.5. configuring po rt 1, 2, and 3 pins as ana- log inputs? on page 207 ). the comparator may also be used as a reset source (see section ?13.5. comparator0 reset? on page 167 ). the output of a comparator can be polled by soft ware, used as an interrupt source, used as a reset source, and/or routed to a port pin. each comparator can be individually enabled and disabled (shutdown). when disabled, the comparator output (if assigned to a port i/o pin via the crossbar) defaults to the logic low state, and its supply current falls to less than 1 a. see section ?17.1.1. crossbar pin assignment and allocation? on page 205 for details on configuring the comparator output via the digital crossbar. the comparator inputs can be externally driven from -0.25 v to (v dd ) + 0.25 v without damage or upset. the complete electrical specifications for the comparator are given in table 11.1. the comparator response time may be configured in software using the cpnmd1-0 bits in register cpt- nmd (see sfr definition 11.2). se lecting a longer response time reduces the amount of power consumed by the comparator. see table 11.1 for complete timing and current consumption specifications. figure 11.1. comparator functional block diagram vdd cptncn reset decision tree + - crossbar interrupt logic q q set clr d q q set clr d (synchronizer) cpn + cpn - cpnen cpnout cpnrif cpnfif cpnhyp1 cpnhyp0 cpnhyn1 cpnhyn0 cptnmd cpnrien cpnfien cpnmd1 cpnmd0 cpn rising-edge interrupt flag cpn falling-edge interrupt flag cpn cp0 + cp0 - cp1 + cp1 - cp2 + cp2 - p2.6 p2.7 p2.2 p2.3 p2.4 p2.5 comparator pin assignments gnd cpn interrupt c8051f040/1/2/3/4/5/6/7 122 rev. 1.5 figure 11.2. compar ator hysteresis plot the hysteresis of the comparator is software-programmable via its comparator control register (cpt- ncn). the user can program both the amount of hyster esis voltage (referred to the input voltage) and the positive and negative-going symmetry of this hysteresis around the threshold voltage. the comparator hysteresis is programmed using bi ts3-0 in the comparator control register cptncn (shown in sfr definition 11.1). the amount of negativ e hysteresis voltage is dete rmined by the settings of the cpnhyn bits. as shown in table 11.1, settings of approximately 20, 10 or 5 mv of negative hysteresis can be programmed, or negative hysteresis can be disa bled. in a similar way, the amount of positive hys- teresis is determined by the setting the cpnhyp bits. comparator interrupts can be generated on either rising- edge and falling-edge outp ut transitions. (for interrupt enable and priority control, see section ?12.3. interrupt handler? on page 153 ). the rising and/ or falling -edge interr upts are enabled using the comparator?s rising/falling edge inte rrupt enable bits (cpnrie and cpnfie) in their respective comparator mode selection register (cptnmd), shown in sfr definition 11.2. these bits allow th e user to control which edge (or both) will cause a comparat or interrupt. however, the comparator interrupt must also be enab led in the extended interrupt enable register (eie1). the cpnfif flag is set to logic 1 upon a comparator falling-ed ge interrupt, and the cpnrif flag is set to logic 1 upon the comparator rising-edge interrupt. once set, these bits remain set until cleared by soft- ware. the output state of a comparator can be obtain ed at any time by reading the cpnout bit. a com- parator is enabled by setting its respective cpnen bit to logic 1, and is disabled by clearing this bit to logic 0.upon enabling a comparator, the output of the comp arator is not immediately valid. before using a com- parator as an interrupt or reset source, software should wait for a minimum of the specified ?power-up time? as specified in table 11.1, ?comparator electrical characteristics,? on page 126. positive hysteresis voltage (programmed with cpnhyp bits) negative hysteresis voltage (programmed by cpnhyn bits) vin- vin+ inputs circuit configuration + _ cpn+ cpn- cpn vin+ vin- out v oh positive hysteresis disabled maximum positive hysteresis negative hysteresis disabled maximum negative hysteresis output v ol c8051f040/1/2/3/4/5/6/7 rev. 1.5 123 11.1. comparator inputs the port pins selected as comparator inputs should be configured as analog inputs in the port 2 input con- figuration register (for details on port configuration, see section ?17.1.3. configuring port pins as digi- tal inputs? on page 206 ). the inputs for comparator are on port 2 as follows: comparator input port pin cp0+ p2.6 cp0? p2.7 cp1+ p2.2 cp1? p2.3 cp2+ p2.4 cp2? p2.5 c8051f040/1/2/3/4/5/6/7 124 rev. 1.5 sfr definition 11.1. cptncn: comparator 0, 1, and 2 control bit7: cpnen: comparat or enable bit. (please see note below.) 0: comparator disabled. 1: comparator enabled. bit6: cpnout: comparator output state flag. 0: voltage on cpn+ < cpn?. 1: voltage on cpn+ > cpn?. bit5: cpnrif: comparator rising-edge interrupt flag. 0: no comparator rising edge interrupt has occurred since this flag was last cleared. 1: comparator rising edge interrupt has occurred. must be cleared by software. bit4: cpnfif: comparator falling-edge interrupt flag. 0: no comparator falling-edge interrupt has occurred since this flag was last cleared. 1: comparator falling-edge interrupt has occurred. must be cleared by software. bits3-2: cpnhyp1-0: comparator positive hysteresis control bits. 00: positive hysteresis disabled. 01: positive hysteresis = 5 mv. 10: positive hysteresis = 10 mv. 11: positive hysteresis = 20 mv. bits1-0: cpnhyn1-0: comparator n egative hysteresis control bits. 00: negative hysteresis disabled. 01: negative hysteresis = 5 mv. 10: negative hysteresis = 10 mv. 11: negative hysteresis = 20 mv. note: upon enabling a comparator, the output of the comparator is not immediately valid. before using a comparator as an interrupt or reset source, software should wait for a minimum of the specified ?power-up time? as specified in table 11.1, ?comparator electrical characteris- tics,? on page 126. r/w r r/w r/w r/w r/w r/w r/w reset value cpnen cpnout cpnrif cpnfif cpnhyp1 cpnhyp0 cpnhyn1 cpnhyn0 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: cpt0cn: 0x88; cpt1cn: 0x88; cpt2cn: 0x88 sfr pages: cpt0cn:page 1;cpt1cn:page 2; cpt2cn:page 3 c8051f040/1/2/3/4/5/6/7 rev. 1.5 125 sfr definition 11.2. cptnmd: comparator mode selection bits7-6: unused. read = 00b, write = don?t care. bit 5: cpnrie: comparator rising-edge interrupt enable bit. 0: comparator rising-edge interrupt disabled. 1: comparator rising-edge interrupt enabled. bit 4: cpnfie: comparator falli ng-edge interrupt enable bit. 0: comparator falling-edge interrupt disabled. 1: comparator falling-edge interrupt enabled. bits3-2: unused. read = 00b, write = don?t care. bits1-0: cpnmd1-cpnmd0: comparator mode select these bits select the response time for the comparator. r/w r/w r/w r/w r r r/w r/w reset value - - cpnrie cpnfie - - cpnmd1 cpnmd0 00000010 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: cpt0md: 0x89; cpt1md: 0x89;cpt2md: 0x89 sfr page: cpt0md:page 1;cpt1md:page 2; cpt2md:page 3 mode cpnmd1 cpnmd0 cpn typical response time 0 0 0 fastest response time 101 ? 210 ? 3 1 1 lowest power consumption c8051f040/1/2/3/4/5/6/7 126 rev. 1.5 table 11.1. comparator electrical characteristics v dd = 3.0 v, ?40 to +85 c unless otherwise specified. parameter conditions min typ max units response time, mode 0 cpn+ ? cpn? = 100 mv ?100 ? ns cpn+ ? cpn? = 10 mv ?250 ? ns response time, mode 1 cpn+ ? cpn? = 100 mv ?175 ? ns cpn+ ? cpn? = 10 mv ?500 ? ns response time, mode 2 cpn+ ? cpn? = 100 mv ?320 ? ns cpn+ ? cpn? = 10 mv ? 1100 ? ns response time, mode 3 cpn+ ? cpn? = 100 mv ?1050 ? ns cpn+ ? cpn? = 10 mv ?5200 ? ns common-mode rejection ratio ?1.5 4 mv/v positive hysteresis 1 cpnhyp1-0 = 00 ?0 1 mv positive hysteresis 2 cpnhyp1-0 = 01 24.5 7 mv positive hysteresis 3 cpnhyp1-0 = 10 49 13 mv positive hysteresis 4 cpnhyp1-0 = 11 10 17 25 mv negative hysteresis 1 cpnhyn1-0 = 00 01mv negative hysteresis 2 cpnhyn1-0 = 01 24.5 7 mv negative hysteresis 3 cpnhyn1-0 = 10 49 13 mv negative hysteresis 4 cpnhyn1-0 = 11 10 17 25 mv inverting or non-inverting inp ut voltage range ?0.25 v dd + 0.25 v input capacitance ?7 ? pf input bias current ?5 0.001 +5 na input offset voltage ?5 +5 mv power supply power supply rejection ?0.1 1 mv/v power-up time ?10 ? s supply current at dc mode 0 ?7.6 ? a mode 1 ?3.2 ? a mode 2 ?1.3 ? a mode 3 ?0.4 ? a c8051f040/1/2/3/4/5/6/7 rev. 1.5 127 12. cip-51 microcontroller the mcu system controller core is the cip-51 microcon troller. the cip-51 is fully compatible with the mcs-51? instruction set; standard 803x/805x assemble rs and compilers can be used to develop soft- ware. the mcu family has a superset of all the peripherals included with a standard 8051. included are five 16-bit counter/time rs (see description in section 23 ), two full-duplex uarts (see description in sec- tion 21 and section 22 ), 256 bytes of internal ram, 128 byte special function register (sfr) address space (see section 12.2.6 ), and 8/4 byte-wide i/o ports (see description in section 17 ). the cip-51 also includes on-chip debug hardware (see description in section 25 ), and interfaces directly with the mcus' analog and digital subsystems providing a complete da ta acquisition or control-system solution in a single integrated circuit. the cip-51 microcontroller core implements the standard 8051 organization and peripherals as well as additional custom peripherals and functions to extend its capability (s ee figure 12.1 for a block diagram). the cip-51 includes the following features: figure 12.1. cip-51 block diagram data bus tmp1 tmp2 prgm. address reg. pc incrementer alu psw data bus data bus memory interface mem_address d8 pipeline buffer data pointer interrupt interface system_irqs debug_irq mem_control control logic a16 program counter (pc) stop clock reset idle power control register data bus sfr bus interface sfr_address sfr_control sfr_write_data sfr_read_data d8 d8 b register d8 d8 accumulator d8 d8 d8 d8 d8 d8 d8 d8 mem_write_data mem_read_data d8 sram address register sram (256 x 8) d8 stack pointer d8 - fully compatible with mcs-51 instruction set - 25 mips peak throughput with 25 mhz clock - 0 to 25 mhz clock frequency - 256 bytes of internal ram - 8/4 byte-wide i/o ports - extended interrupt handler - reset input - power management modes - on-chip debug logic - program and data memory security c8051f040/1/2/3/4/5/6/7 128 rev. 1.5 performance the cip-51 employs a pipelined architecture that grea tly increases its instruction throughput over the stan- dard 8051 architecture. in a standar d 8051, all instructions except for mul and div take 12 or 24 system clock cycles to execute, and usually have a maximum system clock of 12 mhz. by contrast, the cip-51 core executes 70% of its instructions in one or tw o system clock cycles, with no instructions taking more than eight system clock cycles. with the cip-51's maximum system clock at 25 mhz, it has a peak throughput of 25 mips. the cip-51 has a total of 109 instructions. the table below shows the to tal number of instructions that require each execu- tion time. programming and debugging support a jtag-based serial interface is provided for in- system programming of the flash program memory and communication with on-chip debug support logic. the re-programmable flash can also be read and changed a single byte at a time by the application software using the movc an d movx instructions. this feature allows program memory to be used for non-volatile data storage as well as updating program code under software control. the on-chip debug support logic facilitates full speed in-circuit debugging, a llowing the setting of hardware breakpoints and watch points, starting, stopping and si ngle stepping through program execution (including interrupt service routines), examination of the program's call stack, and reading/wr iting the contents of reg- isters and memory. this method of on-chip debug is completely non-intrusive and non-invasive, requiring no ram, stack, timers, or other on-chip resources. the cip-51 is support ed by development tools from silicon labs and third party vendors. silicon labs pro- vides an integrated development environment (ide) including editor, macro assembler, debugger and pro- grammer. the ide's debugger and programmer interface to the cip-51 via its jtag interface to provide fast and efficient in-system devi ce programming and deb ugging. third party macro assemblers and c compilers are also available. clocks to execute 1 2 2/3 3 3/4 4 4/5 5 8 number of instructions 26 50 5 14 7 3 1 2 1 c8051f040/1/2/3/4/5/6/7 rev. 1.5 129 12.1. instruction set the instruction set of the cip-51 system controller is fully compatible with the standard mcs-51? instruc- tion set; standard 8051 development tools can be used to develop software for the cip-51. all cip-51 instructions are the binary and fu nctional equivalent of their mcs-51? counterparts, including opcodes, addressing modes and effect on psw flags. however, in struction timing is different than that of the stan- dard 8051. 12.1.1. instruction and cpu timing in many 8051 implementations, a distinction is ma de between machine cycles and clock cycles, with machine cycles varying from 2 to 12 clock cycles in length. however, the cip-51 implementation is based solely on clock cycle timing. all instructio n timings are specified in terms of clock cycles. due to the pipelined architecture of the cip-51, most instructions execute in the same number of clock cycles as there are program bytes in the instruction. conditional branch instruct ions take one less clock cycle to complete when the branch is not taken as oppo sed to when the branch is taken. table 12.1 is the cip-51 instruction set summary, which includes the mnemonic, number of bytes, and number of clock cycles for each instruction. 12.1.2. movx instruction and program memory in the cip-51, the movx instruction serves three pur poses: accessing on-chip xram, accessing off-chip xram, and accessing on-chip program flash memory. the flash access feature provides a mechanism for user software to update program code and use the program memory space for non-volatile data stor- age (see section ?15. flash memory? on page 179 ). the external memory interface provides a fast access to off-chip xram (or memory-mapped peripherals) via the movx instruction. refer to section ?16. external data me mory interface and on-chip xram? on page 187 for details. table 12.1. cip-51 instruction set summary mnemonic description bytes clock cycles arithmetic operations add a, rn add register to a 1 1 add a, direct add direct byte to a 2 2 add a, @ri add indirect ram to a 1 2 add a, #data add immediate to a 2 2 addc a, rn add register to a with carry 1 1 addc a, direct add direct byte to a with carry 2 2 addc a, @ri add indirect ram to a with carry 1 2 addc a, #data add immediate to a with carry 2 2 subb a, rn subtract register from a with borrow 1 1 subb a, direct subtract direct byte from a with borrow 2 2 subb a, @ri subtract indirect ram from a with borrow 1 2 subb a, #data subtract immediate from a with borrow 2 2 inc a increment a 1 1 inc rn increment register 1 1 inc direct increment direct byte 2 2 inc @ri increment indirect ram 1 2 dec a decrement a 1 1 c8051f040/1/2/3/4/5/6/7 130 rev. 1.5 dec rn decrement register 1 1 dec direct decrement direct byte 2 2 dec @ri decrement indirect ram 1 2 inc dptr increment data pointer 1 1 mul ab multiply a and b 1 4 div ab divide a by b 1 8 da a decimal adjust a 1 1 logical operations anl a, rn and register to a 1 1 anl a, direct and direct byte to a 2 2 anl a, @ri and indirect ram to a 1 2 anl a, #data and immediate to a 2 2 anl direct, a and a to direct byte 2 2 anl direct, #data and immediate to direct byte 3 3 orl a, rn or register to a 1 1 orl a, direct or direct byte to a 2 2 orl a, @ri or indirect ram to a 1 2 orl a, #data or immediate to a 2 2 orl direct, a or a to direct byte 2 2 orl direct, #data or immediate to direct byte 3 3 xrl a, rn exclusive-or register to a 1 1 xrl a, direct exclusive-or direct byte to a 2 2 xrl a, @ri exclusive-or indirect ram to a 1 2 xrl a, #data exclusive-or immediate to a 2 2 xrl direct, a exclusive-or a to direct byte 2 2 xrl direct, #data exclusive-or immediate to direct byte 3 3 clr a clear a 1 1 cpl a complement a 1 1 rl a rotate a left 1 1 rlc a rotate a left through carry 1 1 rr a rotate a right 1 1 rrc a rotate a right through carry 1 1 swap a swap nibbles of a 1 1 data transfer mov a, rn move register to a 1 1 mov a, direct move direct byte to a 2 2 mov a, @ri move indirect ram to a 1 2 mov a, #data move immediate to a 2 2 mov rn, a move a to register 1 1 mov rn, direct move direct byte to register 2 2 mov rn, #data move immediate to register 2 2 mov direct, a move a to direct byte 2 2 mov direct, rn move register to direct byte 2 2 mov direct, direct move direct byte to direct byte 3 3 mov direct, @ri move indirect ram to direct byte 2 2 table 12.1. cip-51 instructi on set summary (continued) mnemonic description bytes clock cycles c8051f040/1/2/3/4/5/6/7 rev. 1.5 131 mov direct, #data move immediate to direct byte 3 3 mov @ri, a move a to indirect ram 1 2 mov @ri, direct move direct byte to indirect ram 2 2 mov @ri, #data move immediate to indirect ram 2 2 mov dptr, #data16 load dptr with 16-bit constant 3 3 movc a, @a+dptr move code byte relative dptr to a 1 3 movc a, @a+pc move code byte relative pc to a 1 3 movx a, @ri move external data (8-bit address) to a 1 3 movx @ri, a move a to external data (8-bit address) 1 3 movx a, @dptr move external data (16-bit address) to a 1 3 movx @dptr, a move a to external data (16-bit address) 1 3 push direct push direct byte onto stack 2 2 pop direct pop direct byte from stack 2 2 xch a, rn exchange register with a 1 1 xch a, direct exchange direct byte with a 2 2 xch a, @ri exchange indirect ram with a 1 2 xchd a, @ri exchange low nibble of indirect ram with a 1 2 boolean manipulation clr c clear carry 1 1 clr bit clear direct bit 2 2 setb c set carry 1 1 setb bit set direct bit 2 2 cpl c complement carry 1 1 cpl bit complement direct bit 2 2 anl c, bit and direct bit to carry 2 2 anl c, /bit and complement of direct bit to carry 2 2 orl c, bit or direct bit to carry 2 2 orl c, /bit or complement of direct bit to carry 2 2 mov c, bit move direct bit to carry 2 2 mov bit, c move carry to direct bit 2 2 jc rel jump if carry is set 2 2/3 jnc rel jump if carry is not set 2 2/3 jb bit, rel jump if direct bit is set 3 3/4 jnb bit, rel jump if direct bit is not set 3 3/4 jbc bit, rel jump if direct bit is set and clear bit 3 3/4 program branching acall addr11 absolute subroutine call 2 3 lcall addr16 long subroutine call 3 4 ret return from subroutine 1 5 reti return from interrupt 1 5 ajmp addr11 absolute jump 2 3 ljmp addr16 long jump 3 4 sjmp rel short jump (relative address) 2 3 jmp @a+dptr jump indirect relative to dptr 1 3 jz rel jump if a equals zero 2 2/3 table 12.1. cip-51 instructi on set summary (continued) mnemonic description bytes clock cycles c8051f040/1/2/3/4/5/6/7 132 rev. 1.5 jnz rel jump if a does not equal zero 2 2/3 cjne a, direct, rel compare direct byte to a and jump if not equal 3 3/4 cjne a, #data, rel compare immediate to a and jump if not equal 3 3/4 cjne rn, #data, rel compare immediate to register and jump if not eq ual 3 3/4 cjne @ri, #data, rel compare immediate to indirect and jump if not eq ual 3 4/5 djnz rn, rel decrement register and jump if not zero 2 2/3 djnz direct, rel decrement direct byte and jump if not zero 3 3/4 nop no operation 1 1 table 12.1. cip-51 instructi on set summary (continued) mnemonic description bytes clock cycles notes on registers, operands and addressing modes: rn - register r0-r7 of the currently selected register bank. @ri - data ram location addressed indirectly through r0 or r1. rel - 8-bit, signed (two?s complement) offset relative to the first byte of the following instruction. used by sjmp and all conditional jumps. direct - 8-bit internal data location?s address. this could be a direct-access data ram location (0x00- 0x7f) or an sfr (0x80-0xff). #data - 8-bit constant #data16 - 16-bit constant bit - direct-accessed bit in data ram or sfr addr11 - 11-bit destination address used by acall and ajmp. the destination must be within the same 2k-byte page of program memory as the first byte of the following instruction. addr16 - 16-bit destination address used by lcall a nd ljmp. the destination may be anywhere within the 64 kb program memory space. there is one unused opcode (0xa5) that performs the same function as nop. all mnemonics copyrighted ? intel corporation 1980. c8051f040/1/2/3/4/5/6/7 rev. 1.5 133 12.2. memory organization the memory organization of the cip-51 system controller is similar to that of a standard 8051. there are two separate memory spaces: program memory and data memory. program and data memory share the same address space but are accessed via different instruction types. there are 256 bytes of internal data memory and 64k bytes of internal program memory address space implemented within the cip-51. the cip-51 memory organization is shown in figure 12.2. figure 12.2. memory map 12.2.1. program memory the cip-51 has a 64 kb program memory space. the mcu implements 64 kb (c8051f040/1/2/3/4/5) and 32 kb (c8051f046/7) of this program memory space as in-system re-programmed flash memory, orga- nized in a contiguous block from addresses 0x0000 to 0xffff (c8051f040/1/2/3/4/5) and 0x0000 to 0x7fff (c8051f046/7). note: 512 bytes from 0xfe00 to 0xffff (c8051f040/1/2/3/4/5 only) of this mem- ory are reserved for factory use and are not available for user program storage. program memory is normally assumed to be read-only . however, the cip-51 can write to program memory by setting the program store write enable bit (psctl.0) and using the movx instru ction. this feature pro- vides a mechanism for the cip-51 to update program code and use the program memory space for non- volatile data storage. refer to section ?15. flash memory? on page 179 for further details. program/data memory (flash) (direct and indirect addressing) 0x00 0x7f upper 128 ram (indirect addressing only) 0x80 0xff special function registers (direct addressing only) data memory (ram) general purpose registers 0x1f 0x20 0x2f bit addressable lower 128 ram (direct and indirect addressing) 0x30 internal data address space external data address space xram - 4096 bytes (accessable using movx instruction) 0x0000 0x0fff off-chip xram space 0x1000 0xffff 64 kb flash (in-system programmable in 512 byte sectors) 0x0000 reserved 0xfe00 0xfdff scrachpad memory (data only) 0x1007f 0x10000 up to 256 sfr pages 1 3 0 2 f c8051f040/1/2/3/4/5 32 kb flash (in-system programmable in 512 byte sectors) 0x0000 reserved 0x8000 0x7fff scrachpad memory (data only) 0x1007f 0x10000 c8051f046/7 c8051f040/1/2/3/4/5/6/7 134 rev. 1.5 12.2.2. data memory the cip-51 implements 256 bytes of internal ram mapped into the data memory space from 0x00 through 0xff. the lower 128 bytes of data memory are used for general purpose registers and scratch pad mem- ory. either direct or indirect addressing may be used to access the lower 128 bytes of data memory. loca- tions 0x00 through 0x1f are addressable as four banks of general purpose register s, each bank consisting of eight byte-wide registers. the next 16 bytes, loca tions 0x20 through 0x2f, may either be addressed as bytes or as 128 bit locations accessible with the direct addressing mode. the upper 128 bytes of data memory are accessible only by indirect addressing. this region occupies the same address space as the special function regist ers (sfr) but is physically separate from the sfr space. the addressing mode used by an instruction when accessing locations above 0x7f determines whether the cpu accesses the upper 128 bytes of data memory space or the sfr?s. instructions that use direct addressing will access the sfr space. instructions using indirect addressing above 0x7f access the upper 128 bytes of data memory. figure 12.2 illustrates the dat a memory organizat ion of the cip-51. 12.2.3. general purpose registers the lower 32 bytes of data memory, locations 0x00 through 0x1f, may be addressed as four banks of gen- eral-purpose registers. each bank consists of eigh t byte-wide registers designated r0 through r7. only one of these banks may be enabled at a time. two bi ts in the program status word, rs0 (psw.3) and rs1 (psw.4), select the active register bank (see descri ption of the psw in sfr de finition 12.8). this allows fast context switching when entering subroutines and interrupt service routines. indirect addressing modes use registers r0 and r1 as index registers. 12.2.4. bit addressable locations in addition to direct access to data memory organized as bytes, the sixteen data memory locations at 0x20 through 0x2f are also accessible as 128 individually addressable bits. each bit has a bit address from 0x00 to 0x7f. bit 0 of the byte at 0x20 has bit address 0x00 while bit 7 of the byte at 0x20 has bit address 0x07. bit 7 of the byte at 0x2f has bit address 0x7f. a bit access is distinguished from a full byte access by the type of instruction used (bit source or destinat ion operands as opposed to a byte source or destina- tion). the mcs-51? assembly language allows an alternate notation for bit addressing of the form xx.b where xx is the byte address and b is the bit position within the byte. for example, the instruction: mov c, 22.3h moves the boolean value at 0x13 (bit 3 of the byte at location 0x22) into the carry flag. 12.2.5. stack a programmer's stack can be located anywhere in the 256 byte data memory. the stack area is designated using the stack pointer (sp, addres s 0x81) sfr. the sp will point to the last location used. the next value pushed on the stack is placed at sp +1 and then sp is incremented. a re set initializes the stack pointer to location 0x07; the first value pushed on the stack is plac ed at location 0x08, which is also the first register (r0) of register bank 1. thus, if more than one register bank is to be used, the sp should be initialized to a location in the data memory not being used for data storage. the stack depth can extend up to 256 bytes. the mcus also have built-in hardware for a stack record which is accessed by the debug logic. the stack record is a 32-bit shift register, where each push or increment sp pushes one record bit onto the register, and each call pushes two record bits onto the regist er. (a pop or decrement sp pops one record bit, c8051f040/1/2/3/4/5/6/7 rev. 1.5 135 and a ret pops two record bits, also.) the stack record circuitry can also detect an overflow or underflow on the 32-bit shift register, and can notify the d ebug software even with the mcu running at speed. 12.2.6. special function registers the direct-access data memory locations from 0x80 to 0xff constitute the sp ecial function registers (sfr?s). the sfr?s provide control and data exchange with the cip-51's resources and peripherals. the cip-51 duplicates the sfr?s found in a typical 8051 implementation as well as implementing additional sfr?s used to configure and access the sub-systems uni que to the mcu. this allows the addition of new functionality while retaining compatibility with the mcs-51 ? instruction set. table 12.2 lists the sfr?s implemented in the cip-51 system controller. the sfr registers are accessed whenever the direct addressing mode is used to access memory loca- tions from 0x80 to 0xff. sfr?s with addresses ending in 0x0 or 0x8 (e.g. p0, tcon, p1, scon, ie, etc.) are bit-addressable as well as byte-addressable. all other sfr?s are byte-addressable only. unoccupied addresses in the sfr space are reserved for future use. accessing t hese areas will have an indeterminate effect and should be avoided. refer to the corres ponding pages of the datasheet, as indicated in table 12.3, for a detailed description of each register. 12.2.6.1. sfr paging the cip-51 features sfr p aging, allowing the device to map many sfr?s into the 0x80 to 0xff memory address space. the sfr memory space has 256 pages . in this way, each memory location from 0x80 to 0xff can access up to 256 sfr?s. th e c8051f04x family of devices utiliz es five sfr pages: 0, 1, 2, 3, and f. sfr pages are selected using the special func tion register page selection register, sfrpage (see sfr definition 12.2). the procedure fo r reading and writing an sfr is as follows: 1. select the appropriate sfr page number using the sfrpage register. 2. use direct accessing mode to read or write t h e special function register (mov instruction). 12.2.6.2. interrupts and sfr paging when an interrupt occurs, the sfr p age regis ter will automatically switch to the sfr page containing the flag bit that caused the interrupt. the automatic sfr page switch function conveniently removes the bur- den of switching sfr pages from the interrupt service routine. upon execut ion of the reti instruction, the sfr page is automatically restored to the sfr page in use prior to the interrupt. this is accomplished via a three-byte sfr page stack . the top byte of the stack is sfrpag e, the current sfr page. the second byte of the sfr page stack is sfrnext. the third, or bottom byte of the sfr page stack is sfrlast. on interrupt, the current sfrpage value is pushed to the sfrnext byte, and the value of sfrnext is pushed to sfrlast. hardware then loads sfrpage with the sfr page containing the flag bit associated with the interrupt. on a return from interrupt, the sfr page stack is popped resulting in the value of sfrn- ext returning to the sfrpage register, thereby restor ing the sfr page context without software interven- tion. the value in sfrlast (0x00 if there is no sfr p age value in the bottom of the stack) of the stack is placed in sfrnext register. if desired, the values stored in sfrnext and sfrlast may be modified during an interrupt, enabling the cpu to return to a different sfr page upon execution of the reti instruc- tion (on interrupt exit). modifying registers in the sfr page stack does not cause a push or pop of the stack. only interrupt calls and returns will cause pu sh/pop operations on the sfr page stack. c8051f040/1/2/3/4/5/6/7 136 rev. 1.5 figure 12.3. sfr page stack automatic hardware switching of the sfr page on interrupts may be enabled or disabled as desired using the sfr automatic page control enable bit located in the sfr page c ontrol register (sfrpgcn). this function defaults to ?enabled? upon reset. in this way, th e autoswitching function will be enabled unless dis- abled in software. a summary of the sfr locations (address and sfr page) is provided in table 12.2. in the form of an sfr memory map. each memory location in the map has an sfr page row, denoting the page in which that sfr resides. note that certain sfr?s are accessible from all sfr pages, and are denoted by the ? (all pages) ? designation. for example, the port i/o registers p0, p1, p2, and p3 all have the ? (all pages) ? designation, indicating these sfr?s are accessible from all sfr pages regardless of the sfrpage regis- ter value. 12.2.6.3. sfr page stack example the following is an example of a c8051f040 device t hat sho ws the operation of the sfr page stack dur- ing interrupts. in this example, the sfr page cont rol is left in the default enabled state (i.e., sfrpgen = 1), and the cip-51 is executing in-line code that is writing values to port 5 (sfr ?p5?, located at address 0xd8 on sfr page 0x0f). the device is also using the programmable counter array (pca) and the 8-bit adc (adc2) window comparator to monitor a voltage. the pca is timing a critical control function in its interrupt service routine (isr), so its interrupt is enabled and is set to high priority. the adc2 is monitoring a voltage that is less important, but to minimize the software overhead its window comparator is being used with an associ- ated isr that is set to low priority. at this point, the sfr page is set to access the port 5 sfr (sfrpage = 0x0f). see figure 12.4 below. sfrnext sfrpage sfrlast interrupt logic c8051f040/1/2/3/4/5/6/7 rev. 1.5 137 figure 12.4. sfr page stack while usi ng sfr page 0x0f to access port 5 while cip-51 executes in-line code (writing values to port 5 in this example), an adc2 window compara- tor interrupt occurs. the cip-51 vectors to the adc2 window comparator isr and pushes the current sfr page value (sfr page 0x0f) into sfrnext in the sfr page stack. the sfr page needed to access adc2?s sfr?s is then automatically placed in the sfrpage register (sfr page 0x02). sfrpage is considered the ?top? of the sfr page stack. software can now access the adc2 sfr?s. software may switch to any sfr page by writing a new value to the sfrpage register at any time during the adc2 isr to access sfr?s that are not on sfr page 0x02. see figure 12.5. 0x0f (port 5) sfrpage sfrlast sfrnext sfr page stack sfr's c8051f040/1/2/3/4/5/6/7 138 rev. 1.5 figure 12.5. sfr page st ack after adc2 window comp arator interrupt occurs while in the adc2 isr, a pca interrupt occurs . recall the pca interrupt is configured as a high priority interrupt, while the adc2 inte rrupt is configured as a low priority interrupt. thus , the cip-51 will now vector to the high priority pca isr. upon doing so, the cip-51 will automatically plac e the sfr page needed to access the pca?s special function registers into the sfrpage register, sfr page 0x00. the value that was in the sfrpage register before the pca interrupt (sfr page 2 for adc2) is pushed down the stack into sfrnext. likewise, the value that was in the sf rnext register before the pca interrupt (in this case sfr page 0x0f for port 5) is pushed down to the sfrlast register, the ?bottom? of the stack. note that a value stor ed in sfrlast (via a previous software write to the sfrlas t register) will be overwritten. see figure 12.6 below. 0x02 (adc2) 0x0f (port 5) sfrpage sfrlast sfrnext sfrpage pushed to sfrnext sfr page 0x02 automatically pushed on stack in sfrpage on adc2 interrupt c8051f040/1/2/3/4/5/6/7 rev. 1.5 139 figure 12.6. sfr page st ack upon pca interrupt occu rring during an adc2 isr on exit from the pca interrupt se rvice routine, the cip-51 will return to the adc2 window comparator isr. on execution of the reti inst ruction, sfr page 0x00 used to access the pca registers will be auto- matically popped off of the sfr page stack, and the contents of the sfrnext register will be moved to the sfrpage register. software in the adc2 isr can continue to access sfr?s as it did prior to the pca interrupt. likewise, the contents of sfrlast are mo ved to the sfrnext register. recall this was the sfr page value 0x0f being used to access port 5 before the adc2 interrupt occurred. see figure 12.7 below. 0x00 (pca) 0x02 (adc2) 0x0f (port 5) sfrpage sfrlast sfrnext sfr page 0x00 automatically pushed on stack in sfrpage on pca interrupt sfrpage pushed to sfrnext sfrnext pushed to sfrlast c8051f040/1/2/3/4/5/6/7 140 rev. 1.5 figure 12.7. sfr page stack u pon return from pca interrupt on the execution of the reti instruction in the adc2 window comparator isr, the value in sfrpage register is overwritten with the cont ents of sfrnext. the cip-51 may now access the port 5 sfr bits as it did prior to the interrupts occurring. see figure 12.8 below. 0x02 (adc2) 0x0f (port 5) sfrpage sfrlast sfrnext sfr page 0x00 automatically popped off of the stack on return from interrupt sfrnext popped to sfrpage sfrlast popped to sfrnext c8051f040/1/2/3/4/5/6/7 rev. 1.5 141 figure 12.8. sfr page stack upon re turn from adc2 window interrupt note that in the above example, all three bytes in the sfr page stack are accessible via the sfrpage, sfrnext, and sfrlast special function registers. if the stack is altered wh ile servicing an in terrupt, it is possible to return to a different sfr page upon interrup t exit than selected prior to the interrupt call. direct access to the sfr page stack can be useful to enable real-time operating systems to control and manage context switching between multiple tasks. push operations on the sfr page stack only occur on interrupt service, and pop operations only occur on interrupt exit (execution on the reti instruction). the automatic switching of the sfrpage and operation of the sfr page stack as described above can be disabled in software by clearing the sfr automatic page enable bit (sfrpgen) in t he sfr page control register (sfr pgcn). see sfr definition 12.1. 0x0f (port 5) sfrpage sfrlast sfrnext sfr page 0x02 automatically popped off of the stack on return from interrupt sfrnext popped to sfrpage c8051f040/1/2/3/4/5/6/7 142 rev. 1.5 sfr definition 12.1. sfr page control register: sfrpgcn sfr definition 12.2. sfr page register: sfrpage bits7-1: reserved. bit0: sfrpgen: sfr automatic page control enable. upon interrupt the c8051 core will vector to the specified interrupt service routine and auto- matically switch the sfr page to the correspo nding peripheral or function?s sfr page. this bit is used to control this autopaging function. 0: sfr automatic paging disabled. c8051 co re will not automatically change to the appro- priate sfr page (i.e., the sfr page that cont ains the sfr?s for the peripheral/function that was the source of the interrupt). 1: sfr automatic paging enabled. upon interrup t, the cip-51 will swit ch the sfr page to the page that contains the sfr?s for the periphera l or function that is the source of the inter- rupt. r r r r r r r r/w reset value -------sfrpgen00000001 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: sfr page: 0x81 all pages bits7-0: sfrpage: sfr page register. byte represents the sfr page the cip-51 uses when reading or modifying sfr?s. sfr page context is retained upon interrupts/return from interrupts in a 3 byte sfr page stack: sfrpage is the first entry, sfrnext is the second, and sfrlast is third entry. the sfrpage, sfrstack, and sfrlast bytes ma y be used alter the context in the sfr page stack. only interrupts and returns from interrupt service routines push and pop the sfr page stack. (see section 12.2.6.2 and section 12.2.6.3 for further information.) write: sets the sfr page read: byte is the sfr page the cip-51 mcu is using. r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: sfr page: 0x84 all pages c8051f040/1/2/3/4/5/6/7 rev. 1.5 143 sfr definition 12.3. sfr next register: sfrnext sfr definition 12.4. sfr last register: sfrlast bits7-0: sfr page context is retained upon interrupts/return from interrupts in a 3 byte sfr page stack: sfrpage is the first entry, sfrnext is the second, and sfrlast is third entry. the sfrpage, sfrstack, and sfrlast bytes ma y be used alter the context in the sfr page stack. only interrupts and returns from interrupt service routines push and pop the sfr page stack. (see section 12.2.6.2 and section 12.2.6.3 for further information.) write: sets the sfr page contained in the second byte of the sfr sta ck. this will cause the sfrpage sfr to have this sfr page value upon a return from interrupt. read: returns the value of the sfr page contained in the second byte of the sfr stack. this is the value that will go to the sfr page register upon a retu rn from interrupt. r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: sfr page: 0x85 all pages bits7-0: sfr page context is retained upon interrupts/return from interrupts in a 3 byte sfr page stack: sfrpage is the first entry, sfrnext is the second, and sfrlast is the third entry. the sfr stack bytes ma y be used alter the context in the sfr page stack, and will not cause the stack to ?push? or ?pop?. only interrupts and returns from the interrupt service routine push and pop the sfr page stack. write: sets the sfr page in the last entry of the sfr stack. this will cause the sfrnext sfr to have this sfr page value upon a return from interrupt. read: returns the value of the sfr page contained in the last entry of the sfr stack. r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: sfr page: 0x86 all pages c8051f040/1/2/3/4/5/6/7 144 rev. 1.5 table 12.2. special function regist er (sfr) memory map a d d r e s s 0(8) 1(9) 2(a) 3(b) 4(c) 5(d) 6(e) 7(f) sfr p a g e f8 spi0cn can0cn p7 pca0l pca0h pca0cpl0 pca0cph0 pca0cpl1 pca0cph1 wdtcn (all pages) 0 1 2 3 f f0 b (all pages) eip1 (all pages) eip2 (all pages) 0 1 2 3 f e8 adc0cn adc2cn p6 pca0cpl2 pca0cph2 pca0cpl3 pca0cph3 pca0cpl4 pca0cph4 rstsrc 0 1 2 3 f e0 acc (all pages) pca0cpl5 xbr0 pca0cph5 xbr1 xbr2 xbr3 eie1 (all pages) eie2 (all pages) 0 1 2 3 f d8 pca0cn can0datl p5 pca0md can0dath pca0cpm0 can0adr pca0cpm1 can0tst pca0cpm2 pca0cpm3 pca0cpm4 pca0cpm5 0 1 2 3 f d0 psw (all pages) ref0cn dac0l dac1l dac0h dac1h dac0cn dac1cn hva0cn 0 1 2 3 f c8 tmr2cn tmr3cn tmr4cn p4 tmr2cf tmr3cf tmr4cf rcap2l rcap3l rcap4l rcap2h rcap3h rcap4h tmr2l tmr3l tmr4l tmr2h tmr3h tmr4h smb0cr 0 1 2 3 f c0 smb0cn can0sta smb0sta smb0dat smb0adr adc0gtl adc2gt adc0gth adc0ltl adc2lt adc0lth 0 1 2 3 f b8 ip (all pages) saden0 amx0cf amx2cf amx0sl amx2sl adc0cf adc2cf amx0prt adc0l adc2 adc0h 0 1 2 3 f 0(8) 1(9) 2(a) 3(b) 4(c) 5(d) 6(e) 7(f) c8051f040/1/2/3/4/5/6/7 rev. 1.5 145 b0 p3 (all pages) flscl flacl 0 1 2 3 f a8 ie (all pages) saddr0 p1mdin p2mdin p3mdin 0 1 2 3 f a0 p2 (all pages) emi0tc emi0cn emi0cf p0mdout p1mdout p2mdout p3mdout 0 1 2 3 f 98 scon0 scon1 sbuf0 sbuf1 spi0cfg spi0dat p4mdout spi0ckr p5mdout p6mdout p7mdout 0 1 2 3 f 90 p1 (all pages) ssta0 sfrpgcn clksel 0 1 2 3 f 88 tcon cpt0cn cpt1cn cpt2cn tmod cpt0md cpt1md cpt2md tl0 oscicn tl1 oscicl th0 oscxcn th1 ckcon psctl 0 1 2 3 f 80 p0 (all pages) sp (all pages) dpl (all pages) dph (all pages) sfrpage (all pages) sfrnext (all pages) sfrlast (all pages) pcon (all pages) 0 1 2 3 f table 12.2. special function regist er (sfr) memory map (continued) a d d r e s s 0(8) 1(9) 2(a) 3(b) 4(c) 5(d) 6(e) 7(f) sfr p a g e 0(8) 1(9) 2(a) 3(b) 4(c) 5(d) 6(e) 7(f) c8051f040/1/2/3/4/5/6/7 146 rev. 1.5 table 12.3. special function registers sfrs are listed in alphabetical order. all undefined sfr locations are reserved. register address sfr page description page no. acc 0xe0 all pages accumulator page 152 adc0cf 0xbc 0 adc0 configuration page 58 1 , page 80 2 adc0cn 0xe8 0 adc0 control page 59 1 , page 81 2 adc0gth 0xc5 0 adc0 greater-than high page 62 1 , page 84 2 adc0gtl 0xc4 0 adc0 greater-than low page 62 1 , page 84 2 adc0h 0xbf 0 adc0 data word high page 60 1 , page 82 2 adc0l 0xbe 0 adc0 data word low page 60 1 , page 82 2 adc0lth 0xc7 0 adc0 less-than high page 62 1 , page 84 2 adc0ltl 0xc6 0 adc0 less-than low page 63 1 , page 85 2 adc2 3 0xbe 2 adc2 data word page 99 adc2cf 3 0xbc 2 adc2 analog multip lexer confi guration page 95 adc2cn 3 0xe8 2 adc2 control page 98 adc2gt 3 0xc4 2 adc2 window comparator greater-than page 100 adc2lt 3 0xc6 2 adc2 window comparator less-than page 100 amx0cf 0xba 0 adc0 multiplexe r configuration page 49 1 , page 71 2 amx0prt 0xbd 0 adc0 port 3 i/o pin select page 51 amx0sl 0xbb 0 adc0 multiplexer channel select page 49 1 , page 71 2 amx2cf 3 0xba 2 adc2 multiplexe r configuration page 97 amx2sl 3 0xbb 2 adc2 multiplexer channel select page 95 b 0xf0 all pages b register page 152 can0adr 0xda 1 can0 address page 213 can0cn 0xf8 1 can0 control page 213 can0dath 0xd9 1 can0 data register high page 212 can0datl 0xd8 1 can0 data register low page 212 can0sta 0xc0 1 can0 status page 214 can0tst 0xdb 1 can0 test register page 214 ckcon 0x8e 0 clock control page 293 clksel 0x97 f oscillator clock selection register page 175 cpt0md 0x89 1 comparator 0 mode selection page 125 cpt1md 0x89 2 comparator 1 mode selection page 125 cpt2md 0x89 3 comparator 2 mode selection page 125 cpt0cn 0x88 1 comparator 0 control page 124 cpt1cn 0x88 2 comparator 1 control page 124 cpt2cn 0x88 3 comparator 2 control page 124 dac0cn 3 0xd4 0 dac0 control page 108 dac0h 3 0xd3 0 dac0 high page 107 dac0l 3 0xd2 0 dac0 low page 107 dac1cn 3 0xd4 1 dac1 control page 110 dac1h 3 0xd3 1 dac1 high byte page 109 c8051f040/1/2/3/4/5/6/7 rev. 1.5 147 dac1l 3 0xd2 1 dac1 low byte page 109 dph 0x83 all pages data pointer high page 150 dpl 0x82 all pages data pointer low page 150 eie1 0xe6 all pages extended interrupt enable 1 page 159 eie2 0xe7 all pages extended interrupt enable 2 page 160 eip1 0xf6 all pages extended interrupt priority 1 page 161 eip2 0xf7 all pages extended interrupt priority 2 page 162 emi0cf 0xa3 0 emif configuration page 190 emi0cn 0xa2 0 external memory interface control page 189 emi0tc 0xa1 0 emif timing control page 195 flacl 0xb7 f flash access limit page 184 flscl 0xb7 0 flash scale page 184 hva0cn 0xd6 0 high voltage differential amp control page 53 1 , page 75 2 ie 0xa8 all pages interrupt enable page 157 ip 0xb8 all pages interrupt priority page 158 oscicl 0x8b f internal oscillator calibration page 174 oscicn 0x8a f internal oscillator control page 174 oscxcn 0x8c f external oscillator control page 176 p0 0x80 all pages port 0 latch page 215 p0mdout 0xa4 f port 0 output mode configuration page 216 p1 0x90 all pages port 1 latch page 216 p1mdin 0xad f port 1 input mode configuration page 217 p1mdout 0xa5 f port 1 output mode configuration page 217 p2 0xa0 all pages port 2 latch page 218 p2mdin 0xae f port 2 input mode configuration page 218 p2mdout 0xa6 f port 2 output mode configuration page 219 p3 0xb0 all pages port 3 latch page 219 p3mdin 0xaf f port 3 input mode configuration page 220 p3mdout 0xa7 f port 3 output mode configuration page 220 p4 4 0xc8 f port 4 latch page 222 p4mdout 4 0x9c f port 4 output mode configuration page 222 p5 4 0xd8 f port 5 latch page 223 p5mdout 4 0x9d f port 5 output mode configuration page 223 p6 4 0xe8 f port 6 latch page 224 p6mdout 4 0x9e f port 6 output mode configuration page 224 p7 4 0xf8 f port 7 latch page 225 p7mdout 4 0x9f f port 7 output mode configuration page 225 pca0cn 0xd8 0 pca control page 312 pca0cph0 0xfc 0 pca capture 0 high page 316 pca0cph1 0xfe 0 pca capture 1 high page 316 pca0cph2 0xea 0 pca capture 2 high page 316 pca0cph3 0xec 0 pca capture 3 high page 316 table 12.3. special functi on registers (continued) sfrs are listed in alphabetical order. all undefined sfr locations are reserved. register address sfr page description page no. c8051f040/1/2/3/4/5/6/7 148 rev. 1.5 pca0cph4 0xee 0 pca capture 4 high page 316 pca0cph5 0xe2 0 pca capture 5 high page 316 pca0cpl0 0xfb 0 pca capture 0 low page 316 pca0cpl1 0xfd 0 pca capture 1 low page 316 pca0cpl2 0xe9 0 pca capture 2 low page 316 pca0cpl3 0xeb 0 pca capture 3 low page 316 pca0cpl4 0xed 0 pca capture 4 low page 316 pca0cpl5 0xe1 0 pca capture 5 low page 316 pca0cpm0 0xda 0 pca module 0 mode register page 314 pca0cpm1 0xdb 0 pca module 1 mode register page 314 pca0cpm2 0xdc 0 pca module 2 mode register page 314 pca0cpm3 0xdd 0 pca module 3 mode register page 314 pca0cpm4 0xde 0 pca module 4 mode register page 314 pca0cpm5 0xdf 0 pca module 5 mode register page 314 pca0h 0xfa 0 pca counter high page 315 pca0l 0xf9 0 pca counter low page 315 pca0md 0xd9 0 pca mode page 313 pcon 0x87 all pages power control page 164 psctl 0x8f 0 program store r/w control page 185 psw 0xd0 all pages program status word page 151 rcap2h 0xcb 0 timer/counter 2 capture/reload high page 301 rcap2l 0xca 0 timer/counter 2 capture/reload low page 301 rcap3h 0xcb 1 timer/counter 3 capture/reload high page 301 rcap3l 0xca 1 timer/counter 3 capture/reload low page 301 rcap4h 0xcb 2 timer/counter 4 capture/reload high page 301 rcap4l 0xca 2 timer/counter 4 capture/reload low page 301 ref0cn 0xd1 0 programmable volta g e reference control page 114 4 , page 118 5 rstsrc 0xef 0 reset source register page 170 saddr0 0xa9 0 uart 0 slave address page 276 saden0 0xb9 0 uart 0 slave address enable page 276 sbuf0 0x99 0 uart 0 data buffer page 276 sbuf1 0x99 1 uart 1 data buffer page 283 scon0 0x98 0 uart 0 control page 274 scon1 0x98 1 uart 1 control page 282 sfrpage 0x84 all pages sfr page register page 142 sfrpgcn 0x96 f sfr page control register page 142 sfrnext 0x85 all pages sfr next page stack access register page 143 sfrlast 0x86 all pages sfr last page stack access register page 143 smb0adr 0xc3 0 smbus slave address page 250 smb0cn 0xc0 0 smbus control page 247 smb0cr 0xcf 0 smbus clock rate page 248 smb0dat 0xc2 0 smbus data page 249 smb0sta 0xc1 0 smbus status page 251 sp 0x81 all pages stack pointer page 150 table 12.3. special functi on registers (continued) sfrs are listed in alphabetical order. all undefined sfr locations are reserved. register address sfr page description page no. c8051f040/1/2/3/4/5/6/7 rev. 1.5 149 spi0cfg 0x9a 0 spi configuration page 261 spi0ckr 0x9d 0 spi clock rate control page 263 spi0cn 0xf8 0 spi control page 262 spi0dat 0x9b 0 spi data page 264 ssta0 0x91 0 uart0 status and clock selection page 275 tcon 0x88 0 timer/counter control page 291 th0 0x8c 0 timer/counter 0 high page 294 th1 0x8d 0 timer/counter 1 high page 294 tl0 0x8a 0 timer/counter 0 low page 293 tl1 0x8b 0 timer/counter 1 low page 294 tmod 0x89 0 timer/counter mode page 292 tmr2cf 0xc9 0 timer/counter 2 configuration page 300 tmr2cn 0xc8 0 timer/counter 2 control page 299 tmr2h 0xcd 0 timer/counter 2 high page 302 tmr2l 0xcc 0 timer/counter 2 low page 301 tmr3cf 0xc9 1 timer/counter 3 configuration page 300 tmr3cn 0xc8 1 timer 3 control page 299 tmr3h 0xcd 1 timer/counter 3 high page 302 tmr3l 0xcc 1 timer/counter 3 low page 301 tmr4cf 0xc9 2 timer/counter 4 configuration page 300 tmr4cn 0xc8 2 timer/counter 4 control page 299 tmr4h 0xcd 2 timer/counter 4 high page 302 tmr4l 0xcc 2 timer/counter 4 low page 301 wdtcn 0xff all pages watchdog timer control page 169 xbr0 0xe1 f port i/o crossbar control 0 page 212 xbr1 0xe2 f port i/o crossbar control 1 page 213 xbr2 0xe3 f port i/o crossbar control 2 page 214 xbr3 0xe4 f port i/o crossbar control 3 page 215 0x97, 0xa2, 0xb3, 0xb4, 0xce, 0xdf reserved notes: 1. re fers to a register in the c8051f040 only. 2. re fers to a register in the c8051f041 only. 3. re fers to a register in c8051f040/1/2/3 only. 4. re fers to a register in the c8051f040/2/4/6 only. 5. re fers to a register in the c8051f041/3/5/7 only. table 12.3. special functi on registers (continued) sfrs are listed in alphabetical order. all undefined sfr locations are reserved. register address sfr page description page no. c8051f040/1/2/3/4/5/6/7 150 rev. 1.5 12.2.7. register descriptions following are descriptions of sfrs related to the operati on of the cip-51 system controller. reserved bits should not be set to logic 1. future product versions may use these bits to implement new features, in which case the reset value of the bi t will be logic 0, selecting the featur e's default state. detailed descrip- tions of the remaining sfrs are included in the se ctions of the data sheet associated with their corre- sponding system function. sfr definition 12.5. sp: stack pointer sfr definition 12.6. dpl: data pointer low byte sfr definition 12.7. dph: data pointer high byte bits7-0: sp: stack pointer. the stack pointer holds the location of the top of the stack. the stack pointer is incremented before every push operation. the sp r egister defaults to 0x07 after reset. r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000111 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: sfr page: 0x81 all pages bits7-0: dpl: data pointer low. the dpl register is the low byte of the 16-b it dptr. dptr is used to access indirectly addressed xram and flash memory. r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: sfr page: 0x82 all pages bits7-0: dph: data pointer high. the dph register is the high byte of the 16-b it dptr. dptr is used to access indirectly addressed xram and flash memory. r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: sfr page: 0x83 all pages c8051f040/1/2/3/4/5/6/7 rev. 1.5 151 sfr definition 12.8. psw: program status word bit7: cy: carry flag. this bit is set when the last arithmetic operat ion resulted in a carry (addition) or a borrow (subtraction). it is cleared to 0 by all other arithmetic operations. bit6: ac: auxiliary carry flag this bit is set when the last arithmetic operati on resulted in a carry into (addition) or a borrow from (subtraction) the high order nibble. it is cleared to 0 by all other arithmetic operations. bit5: f0: user flag 0. this is a bit-addressable, general purpose flag for use under software control. bits4-3: rs1-rs0: register bank select. these bits select which register ban k is used during register accesses. ? bit2: ov: overflow flag. this bit is set to 1 under the following circumstances: ? an add, addc, or subb instruction causes a sign-change overflow. ? a mul instruction results in an overflow (result is greater than 255). ? a div instruction causes a divide-by-zero condition. the ov bit is cleared to 0 by the add, ad dc, subb, mul, and div instructions in all ? other cases. bit1: f1: user flag 1. this is a bit-addressable, general purpose flag for use under software control. bit0: parity: parity flag. this bit is set to 1 if the sum of the eight bits in the accumulator is odd and cleared if the sum is even. r/w r/w r/w r/w r/w r/w r/w r/w reset value cy ac f0 rs1 rs0 ov f1 parity 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 bit addressable sfr address: sfr page: 0xd0 all pages rs1 rs0 register bank address 0 0 0 0x00?0x07 0 1 1 0x08?0x0f 1 0 2 0x10?0x17 1 1 3 0x18?0x1f c8051f040/1/2/3/4/5/6/7 152 rev. 1.5 sfr definition 12.9. acc: accumulator sfr definition 12.10. b: b register bits7-0: acc: accumulator. this register is the accumulator for arithmetic operations. r/w r/w r/w r/w r/w r/w r/w r/w reset value acc.7 acc.6 acc.5 acc.4 acc.3 acc.2 acc.1 acc.0 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 bit addressable sfr address: sfr page: 0xe0 all pages bits7-0: b: b register. this register serves as a second accumu lator for certain arithmetic operations. r/w r/w r/w r/w r/w r/w r/w r/w reset value b.7 b.6 b.5 b.4 b.3 b.2 b.1 b.0 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 bit addressable sfr address: sfr page: 0xf0 all pages c8051f040/1/2/3/4/5/6/7 rev. 1.5 153 12.3. interrupt handler the cip-51 includes an extended interrupt system supp orting a total of 20 interrupt sources with two prior- ity levels. the allocation of interrupt sources between on-chip periph erals and external inputs pins varies according to the specific version of the device. each interrupt source has one or more associated interrupt- pending flag(s) located in an sfr. when a peripheral or external source meets a valid interrupt condition, the associated interrupt-pending flag is set to logic 1. if interrupts are enabled for the source, an interrupt req uest is generated when the interrupt-pending flag is set. as soon as execution of the current instructio n is complete, the cpu generates an lcall to a prede- termined address to begin execution of an interrupt se rvice routine (isr). each isr must end with an reti instruction, which returns program execution to the next instruction that would have been executed if the interrupt request had not occurred. if interrupts are not enabled, the interrupt-pending flag is ignored by the hardware and program execution continues as normal. the interrupt-pending flag is set to logic 1 regard- less of the interrupt's enable/disable state. each interrupt source can be individually enabled or disabled through the use of an associated interrupt enable bit in an sfr (ie-eie2). ho wever, interrupts must first be globally enabled by setting the ea bit (ie.7) to logic 1 before the individual interrupt enabl es are recognized. setting the ea bit to logic 0 disables all interrupt sources regardless of the individual interrupt-enable settings. note: any instruction that clears the ea bit should be immediately followed by an instruction that has two or more opcode bytes. for example: ? // in 'c': ? ea = 0; // clear ea bit ? ea = 0; // ... followed by another 2-byte opcode ? ? ; in assembly: ? clr ea ; clear ea bit ? clr ea ; ... followed by another 2-byte opcode ? if an interrupt is posted during the execution phase of a "clr ea" opcode (or an y instruction which clears the ea bit), and the instruction is followed by a single-cycle instruction, the interrupt may be taken. how- ever, a read of the ea bit will return a '0' inside the inte rrupt service routin e. when the "clr ea" opcode is followed by a multi-cycle instruct ion, the interrupt will not be taken. some interrupt-pending flags are automatically cleare d by the hardware when the cpu vectors to the isr. however, most are not cleared by the hardware and must be cleared by software before returning from the isr. if an interrupt-pending flag remains set after the cpu completes the return-from-interrupt (reti) instruction, a new interr upt request will be gen erated immediately and the cpu will re-enter the isr after the completion of th e next instruction. 12.3.1. mcu interrupt sources and vectors the mcus support 20 interrupt sources. software can simulate an interrupt event by setting any interrupt- pending flag to logic 1. if interrupts are enabled for the flag, an interrupt request will be generated and the cpu will vector to the isr address associated with the interrupt-pending flag. mcu interrupt sources, associated vector addresses, priority order and cont rol bits are summarized in table 12.4. refer to the datasheet section associated with a particular on-chip peripheral for information regarding valid interrupt conditions for the peripheral and the behavior of its interrupt-pending flag(s). c8051f040/1/2/3/4/5/6/7 154 rev. 1.5 12.3.2. external interrupts the external interrupt sources (/int0 and /int1) are c onfigurable as active-low level-sensitive or active- low edge-sensitive inputs depending on the setting of bits it0 (tcon.0) and it1 (tcon.2). ie0 (tcon.1) and ie1 (tcon.3) serve as the interrupt-pending flag for the /int0 and /int1 external interrupts, respec- tively. if an /int0 or /int1 external interrupt is configured as edge-sensitive, the corresponding interrupt- pending flag is automatically cleare d by the hardware when the cpu vectors to the isr. when configured as level sensitive, the inte rrupt-pending flag follows the state of the external interrupt's input pin. the exter- nal interrupt source must hold the input active until the interrupt request is recogniz ed. it must then deacti- vate the interrupt request before execution of the isr completes or another in terrupt request will be generated. table 12.4. interrupt summary interrupt source interrupt vector priority order pending flag bit addressable? cleared by hw? sfrpage (sfrpgen = 1) enable flag priority control reset 0x0000 to p none n/a n/a 0 always enabled always highe st external interrupt 0 (/int0) 0x0003 0 ie0 (tcon.1) y y 0 ex0 (ie.0) px0 (ip.0) timer 0 overflow 0x000b 1 tf0 (tcon.5) y y 0 et0 (ie.1) pt0 (ip.1) external interrupt 1 (/int1) 0x0013 2 ie1 (tcon.3) y y 0 ex1 (ie.2) px1 (ip.2) timer 1 overflow 0x001b 3 tf1 (tcon.7) y y 0 et1 (ie.3) pt1 (ip.3) uart0 0x0023 4 ri0 (scon0.0) ti0 (scon0.1) y 0 es0 (ie.4) ps0 (ip.4) timer 2 0x002b 5 tf2 (tmr2cn.7) y 0 et2 (ie.5) pt2 (ip.5) serial peripheral interf ace 0x0033 6 spif (spi0cn.7) wcol (spi0cn.6) modf (spi0cn.5) rxovrn (s pi0cn.4) y 0 espi0 (eie1.0) pspi0 (eip1.0) smbus interface 0x003b 7 si (smb0cn.3) y 0 esmb0 (eie1.1) psmb0 (eip1.1) adc0 window comp arator 0x0043 8 ad0wint (a dc0cn.2) y 0 ewadc0 (eie1.2) pwadc0 (eip1.2) programmable coun ter array 0x004b 9 cf (pca0cn.7) ccfn (pca0cn.n) y 0 epca0 (eie1.3) ppca0 (eip1.3) comparator 0 0x0053 10 cp0fif/cp0rif (c pt0cn.4/.5) 1 cp0ie (eie1.4) pcp0 (eip1.4) c8051f040/1/2/3/4/5/6/7 rev. 1.5 155 comparator 1 0x005b 11 cp1fif/cp1rif (c pt1cn.4/.5) 2 cp1ie (eie1.5) pcp1 (eip1.5) comparator 2 0x0063 12 cp2fif/cp2rif (c pt2cn.4/.5) 3 cp2ie (eie1.6) pcp2 (eip1.6) timer 3 0x0073 14 tf3 (tmr3cn.7) 1 et3 (eie2.0) pt3 (eip2.0) adc0 end of conver sion 0x007b 15 adc0int (a dc0cn.5) y 0 eadc0 (eie2.1) padc0 (eip2.1) timer 4 0x0083 16 tf4 (tmr4cn.7) 2 et4 (eie2.2) pt4 (eip2.2) adc2 window comp arator 0x0093 17 ad2wint (adc2cn.0) 2 ewadc2 (eie2.3) pwadc2 (eip2.3) adc2 end of conver sion 0x008b 18 adc2int (a dc1cn.5) 2 eadc1 (eie2.4) padc1 (eip2.4) can interrupt 0x009b 19 can0cn.7 y 1 ecan0 (eie2.5) pcan0 (eip2.5) uart1 0x00a3 20 ri1 (scon1.0) ti1 (scon1.1) 1 es1 (eie2.6) ps1 (eip2.6) table 12.4. interrupt summary (continued) interrupt source interrupt vector priority order pending flag bit addressable? cleared by hw? sfrpage (sfrpgen = 1) enable flag priority control c8051f040/1/2/3/4/5/6/7 156 rev. 1.5 12.3.3. interrupt priorities each interrupt source can be individually programmed to one of two priority levels: low or high. a low prior- ity interrupt service routine can be pree mpted by a high priority interrupt. a high priority interrupt cannot be preempted. each interrupt has an associated interrupt priority bit in an sfr (ip-eip2) used to configure its priority level. low priority is the default. if two interrupts are recognized simultaneously, the interrupt with the higher priority is serviced first. if both interrupts have the same priority level, a fixed priority order is used to arbitrate, given in table 12.4. 12.3.4. interrupt latency interrupt response time depends on the state of the cpu when the interrupt occurs. pending interrupts are sampled and priority decoded each system clock cycle. the fast est possible response time is 5 system clock cycles: 1 clock cycle to detect the interrupt and 4 clock cycles to co mplete the lcall to the isr. if an interrupt is pending when a reti is executed, a single instruction is executed before an lcall is made to service the pending interrupt. therefore, the slowest response time for an interrupt (when no other inter- rupt is currently being serviced or the new interrupt is of greater priority) occu rs when the cpu is perform- ing an reti instruction followed by a div as the next instruction. in this case, the response time is 18 system clock cycles: 1 clock cycle to detect the in terrupt, 5 clock cycles to execute the reti, 8 clock cycles to complete the div instruction and 4 clock cycl es to execute the lcall to the isr. if the cpu is executing an isr for an interr upt with equal or higher pr iority, the new interrupt will not be serviced until the current isr completes, including the reti and following instruction. 12.3.5. interrupt register descriptions the sfrs used to enable the interrupt sources and set t heir priority level are described below. refer to the datasheet section associated with a particular on-chip peripheral for information regarding valid interrupt conditions for the peripheral and the behavior of its interrupt-pending flag(s). c8051f040/1/2/3/4/5/6/7 rev. 1.5 157 sfr definition 12.11. ie: interrupt enable bit7: ea: enable all interrupts. this bit globally enables/disabl es all interrupts. it overrides the individual interrupt mask set- tings. 0: disable all interrupt sources. 1: enable each interrupt accord ing to its individual mask setting. bit6: iegf0: general purpose flag 0. this is a general purpose flag for use under software control. bit5: et2: enabler timer 2 interrupt. this bit sets the masking of the timer 2 interrupt. 0: disable timer 2 interrupt. 1: enable interrupt requests generated by the tf2 flag. bit4: es0: enable uart0 interrupt. this bit sets the masking of the uart0 interrupt. 0: disable uart0 interrupt. 1: enable ua rt0 interrupt. bit3: et1: enable timer 1 interrupt. this bit sets the masking of the timer 1 interrupt. 0: disable all ti mer 1 interrupt. 1: enable interrupt requests generated by the tf1 flag. bit2: ex1: enable exte rnal interrupt 1. this bit sets the masking of external interrupt 1. 0: disable external interrupt 1. 1: enable interrupt requests generated by the /int1 pin. bit1: et0: enable timer 0 interrupt. this bit sets the masking of the timer 0 interrupt. 0: disable all ti mer 0 interrupt. 1: enable interrupt requests generated by the tf0 flag. bit0: ex0: enable exte rnal interrupt 0. this bit sets the masking of external interrupt 0. 0: disable external interrupt 0. 1: enable interrupt requests generated by the /int0 pin. r/w r/w r/w r/w r/w r/w r/w r/w reset value ea iegf0 et2 es0 et1 ex1 et0 ex0 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 bit addressable sfr address: sfr page: 0xa8 all pages c8051f040/1/2/3/4/5/6/7 158 rev. 1.5 sfr definition 12.12. ip: interrupt priority bits7-6: unused. read = 11b, write = don't care. bit5: pt2: timer 2 interr upt priority control. this bit sets the priority of the timer 2 interrupt. 0: timer 2 interrupt priority set to low priority level. 1: timer 2 interrupts set to high priority level. bit4: ps0: uart0 interrupt priority control. this bit sets the priority of the uart0 interrupt. 0: uart0 interrupt priority set to low priority level. 1: uart0 interrupts set to high priority level. bit3: pt1: timer 1 interr upt priority control. this bit sets the priority of the timer 1 interrupt. 0: timer 1 interrupt priority set to low priority level. 1: timer 1 interrupts set to high priority level. bit2: px1: external interr upt 1 priority control. this bit sets the priority of the ex ternal interrupt 1 interrupt. 0: external interrupt 1 priority set to low priority level. 1: external interrupt 1 set to high priority level. bit1: pt0: timer 0 interr upt priority control. this bit sets the priority of the timer 0 interrupt. 0: timer 0 interrupt priority set to low priority level. 1: timer 0 interrupt set to high priority level. bit0: px0: external interr upt 0 priority control. this bit sets the priority of the ex ternal interrupt 0 interrupt. 0: external interrupt 0 priority set to low priority level. 1: external interrupt 0 set to high priority level. r/w r/w r/w r/w r/w r/w r/w r/w reset value - - pt2 ps0 pt1 px1 pt0 px0 11000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 bit addressable sfr address: sfr page: 0xb8 all pages c8051f040/1/2/3/4/5/6/7 rev. 1.5 159 sfr definition 12.13. eie1: extended interrupt enable 1 bit7: reserved. read = 0b, write = don?t care. bit6: cp2ie: enable comparator (cp2) interrupt. this bit sets the masking of the cp2 interrupt. 0: disable cp2 interrupts. 1: enable interrupt requests generated by the cp2if flag. bit6: cp1ie: enable comparator (cp1) interrupt. this bit sets the masking of the cp1 interrupt. 0: disable cp1 interrupts. 1: enable interrupt requests generated by the cp1if flag. bit6: cp0ie: enable comparator (cp0) interrupt. this bit sets the masking of the cp0 interrupt. 0: disable cp0 interrupts. 1: enable interrupt requests generated by the cp0if flag. bit3: epca0: enable programmable counter array (pca0) interrupt. this bit sets the masking of the pca0 interrupts. 0: disable all pc a0 interrupts. 1: enable interrupt requests generated by pca0. bit2: ewadc0: enable window comparison adc0 interrupt. this bit sets the masking of adc0 window comparison interrupt. 0: disable adc0 window comparison interrupt. 1: enable interrupt requests generated by adc0 window comparisons. bit1: esmb0: enable system management bus (smbus0) interrupt. this bit sets the masking of the smbus interrupt. 0: disable all smbus interrupts. 1: enable interrupt requests generated by the si flag. bit0: espi0: enable serial peripheral interfac e (spi0) in terrupt. this bit sets the masking of spi0 interrupt. 0: disable all spi0 interrupts. 1: enable interrupt requests generated by the spi0 flag. r/w r/w r/w r/w r/w r/w r/w r/w reset value cp2ie cp1ie cp0ie epca0 ewadc0 esmb0 espi0 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: sfr page: 0xe6 all pages c8051f040/1/2/3/4/5/6/7 160 rev. 1.5 sfr definition 12.14. eie2: extended interrupt enable 2 bit7: reserved bit6: es1: enable uart1 interrupt. this bit sets the masking of the uart1 interrupt. 0: disable uart1 interrupt. 1: enable ua rt1 interrupt. bit5: ecan0: enable can controller interrupt. this bit sets the masking of the can controller interrupt. 0: disable can co ntroller interrupt. 1: enable interrupt requests generated by the can controller. bit4: eadc2: enable adc2 end of conversion interrupt (c8051f040/1/2/3 only). this bit sets the masking of the adc2 end of conversion interrupt. 0: disable adc2 end of conversion interrupt. 1: enable interrupt requests generated by the adc2 end of conversion interrupt. bit3: ewadc2: enable window comparison adc2 interrupt (c8051f040/1/2/3 only). this bit sets the masking of adc2 window comparison interrupt. 0: disable adc2 window comparison interrupt. 1: enable interrupt requests generated by adc2 window comparisons. bit2: et4: enable timer 4 interrupt this bit sets the masking of the timer 4 interrupt. 0: disable timer 4 interrupt. 1: enable interrupt requests generated by the tf4 flag. bit1: eadc0: enable adc0 end of conversion interrupt. this bit sets the masking of the adc0 end of conversion interrupt. 0: disable adc0 co nversion interrupt. 1: enable interrupt requests generated by the adc0 conversion interrupt. bit0: et3: enable timer 3 interrupt. this bit sets the masking of the timer 3 interrupt. 0: disable all ti mer 3 interrupts. 1: enable interrupt requests generated by the tf3 flag. r/w r/w r/w r/w r/w r/w r/w r/w reset value - es1 ecan0 eadc2 ewadc2 et4 eadc0 et3 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: sfr page: 0xe7 all pages c8051f040/1/2/3/4/5/6/7 rev. 1.5 161 sfr definition 12.15. eip1: extended interrupt priority 1 bit7: reserved. bit6: pcp2: comparator2 (cp2) interrupt prio rity control. this bit sets the priority of the cp2 interrupt. 0: cp2 interrupt set to low priority level. 1: cp2 interrupt set to high priority level. bit5: pcp1: comparator1 (cp1) interrupt prio rity control. this bit sets the priority of the cp1 interrupt. 0: cp1 interrupt set to low priority level. 1: cp1 interrupt set to high priority level. bit4: pcp0: comparator0 (cp0) interrupt prio rity control. this bit sets the priority of the cp0 interrupt. 0: cp0 interrupt set to low priority level. 1: cp0 interrupt set to high priority level. bit3: ppca0: programmable counter arra y (pca0) interrupt priority control. this bit sets the priority of the pca0 interrupt. 0: pca0 interrupt set to low priority level. 1: pca0 interrupt set to high priority level. bit2: pwadc0: adc0 window comparator interrupt priority control. this bit sets the priority of the adc0 window interrupt. 0: adc0 window interrupt set to low priority level. 1: adc0 window interrupt set to high priority level. bit1: psmb0: system management bus (s mbus0) interrupt priority control. this bit sets the priority of the smbu s0 interrupt. 0: smbus interr upt set to low priority level. 1: smbus interrup t set to high priority level. bit0: pspi0: serial periph eral interface (spi0) in terrupt priority control. this bit sets the priority of the spi0 interrupt. 0: spi0 interrupt set to low priority level. 1: spi0 interrupt set to high priority level. r/w r/w r/w r/w r/w r/w r/w r/w reset value - pcp2 pcp1 pcp0 ppca0 pwadc0 psmb0 pspi0 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: sfr page: 0xf6 all pages c8051f040/1/2/3/4/5/6/7 162 rev. 1.5 sfr definition 12.16. eip2: extended interrupt priority 2 bit7: reserved. bit6: ep1: uart1 interrupt priority control. this bit sets the priority of the uart1 interrupt. 0: uart1 interrupt set to low level. 1: uart1 interrupt set to high level. bit5: pcan0: can interrup t priority control. this bit sets the priority of the can interrupt. 0: can interrupt set to low priority level. 1: can interrupt set to high priority level. bit4: padc2: adc2 end of conv ersion interrupt priority co ntrol (c8051f040/1/2/3 only). this bit sets the priority of the adc2 end of conversion interrupt. 0: adc2 end of conversion interrupt set to low level. 1: adc2 end of conversion interrupt set to low level. bit3: pwadc2: adc2 window comparator interr upt priority control (c 8051f040/1/2/3 only). 0: adc2 window interr upt set to low level. 1: adc2 window interr upt set to high level. bit2: pt4: timer 4 interr upt priority control. this bit sets the priority of the timer 4 interrupt. 0: timer 4 interrupt set to low level. 1: timer 4 interrupt set to low level. bit1: padc0: adc end of conversion interrupt priority control. this bit sets the priority of the adc0 end of conversion interrupt. 0: adc0 end of conversion inte rrupt set to low priority level. 1: adc0 end of conversion interrupt set to high priority level. bit0: pt3: timer 3 interr upt priority control. this bit sets the priority of the timer 3 interrupts. 0: timer 3 interrupt set to low priority level. 1: timer 3 interrupt set to high priority level. r/w r/w r/w r/w r/w r/w r/w r/w reset value - ep1 px7 padc2 pwadc2 pt4 padc0 pt3 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: sfr page: 0xf7 all pages c8051f040/1/2/3/4/5/6/7 rev. 1.5 163 12.17. power management modes the cip-51 core has two software programmable power management modes: idle and stop. idle mode halts the cpu while leaving the extern al peripherals and internal clocks active. in stop mode, the cpu is halted, all interrupts and timers (e xcept the missing clock detector) are in active, and the internal oscillator is stopped. since clocks are running in idle mode, power consumption is dependent upon the system clock frequency and the number of peripherals left in active mode before entering idle. stop mode consumes the least power. sfr definition 12.18 describes the powe r control register (pcon) used to control the cip- 51's power management modes. although the cip-51 has idle and stop modes built in (as with any standard 8051 architecture), power management of the entire mcu is better accomplished by enabling/disabling individual peripherals as needed. each analog peripheral can be disabled when not in use and put into low power mode. digital peripherals, such as timers or serial buses, draw littl e power whenever they are not in use. turning off the oscillator saves even more power, but requires a reset to restart the mcu. 12.17.1.idle mode setting the idle mode select bit (pcon.0) causes the cip-51 to halt the cpu and enter idle mode as soon as the instruction that sets the bit completes. all internal registers and memory maintain their original data. all analog and digital peripherals can remain active during idle mode. idle mode is terminated when an enabled interrupt or /rst is asserted. the assertion of an enabled inter- rupt will cause the idle m ode selection bit (pcon.0) to be cleared and the cpu to resume operation. the pending interrupt will be serviced and the next instru ction to be executed after the return from interrupt (reti) will be the instruction immediat ely following the one that set the idle mode select bit. if idle mode is terminated by an internal or external reset, the cip-51 performs a normal reset sequence and begins pro- gram execution at address 0x0000. if enabled, the wdt will eventually cause an internal watchdog reset and thereby terminate the idle mode. this feature protects the system from an unintended permanent shutdown in the event of an inadvertent write to the pcon register. if this behavior is not desired, the wdt may be disabled by software prior to entering the idle mode if the wdt was initially configured to allow this operation. this provides the oppor- tunity for additional power savings, allowing the system to remain in the idle mode indefinitely, waiting for an external stimulus to wake up the system. refer to section 13.7 for more information on the use and configuration of the wdt. note: any instruction that sets the idle bit should be i mmediately followed by an instruction that has 2 or more opcode bytes. for example: // in 'c': ? pcon |= 0x01; // set idle bit ? pcon = pcon; // ... followed by a 3-cycle dummy instruction ? ? ; in assembly: ? orl pcon, #01h ; set idle bit ? mov pcon, pcon ; ... followed by a 3-cycle dummy instruction if the instruction following the write of the idle bit is a single-byte instruct ion and an interrupt occurs during the execution phase of the instructio n that sets the idle bit, the cpu may not wake from idle mode when a future interrupt occurs. c8051f040/1/2/3/4/5/6/7 164 rev. 1.5 12.17.2.stop mode setting the stop mode select bit (pcon.1) causes the ci p-51 to enter stop mode as soon as the instruc- tion that sets the bit completes. in stop mode, the cpu and internal oscillators are stopped, effectively shutting down all digital peripherals. each analog peri pheral must be shut down individually prior to enter- ing stop mode. stop mode can only be terminated by an internal or external rese t. on reset, the cip-51 performs the normal reset sequence and begi ns program execution at address 0x0000. if enabled, the missing clock detect or will cause an internal reset and ther eby terminate th e stop mode. the missing clock detector should be disabled if the cpu is to be put to sleep for longer than the mcd timeout of 100 s. sfr definition 12.18. pcon: power control bits7-3: reserved. bit1: stop: stop mode select. writing a ?1? to this bit will place the cip-51 into stop mode. this bit will always read ?0?. 0: no effect. 1: cip-51 forced into po wer-down mode. (turns of f internal oscillator). bit0: idle: idle mode select. writing a ?1? to this bit will place the cip-51 into idle mode. this bit will always read ?0?. 0: no effect. 1: cip-51 forced into idle mode. (shuts off clock to cpu, but clock to timers, interrupts, and all peripherals remain active.) r/w r/w r/w r/w r/w r/w r/w r/w reset value ? ? ? ? ? ? stop idle 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: sfr page: 0x87 all pages c8051f040/1/2/3/4/5/6/7 rev. 1.5 165 13. reset sources reset circuitry allows the controller to be easily placed in a predefined default condition. on entry to this reset state, th e following occur: ? cip-51 halts program execution ? special function registers (sfrs) are initialized to their defined reset values ? external port pins are forced to a known state ? interrupts and timers are disabled. all sfrs are reset to the predefined values noted in the sfr detailed descriptions. the contents of internal d ata memory are unaffected during a reset; any prev iously stored data is preserved. however, since the stack pointer sfr is reset, the stack is effectively lo st even though the data on the stack are not altered. the i/o port latches are reset to 0xff (all logic 1s), ac tivating internal weak pullups which take the external i/o pins to a high state. for v dd monitor resets, the /rst pin is driven low until the end of the v dd reset timeout. on exit from the reset state, the program counter (pc) is reset, and the system clock defaults to the inter- nal oscillator running at its lowe st frequency. refe r to section ? 14. oscillators ? on page 173 for informa- tion on selecting and conf iguring the system clock source. the watchdog timer is enabled using its longest timeout interval (see section ? 13.7. watchdog timer reset ? on page 167 ). once the system clock source is stable, program execution begins at location 0x0000. there are seven sources for putting the mcu into the re set state: power-on, power-fail, external /rst pin, external cnvstr0 signal, software command, comp arator0, missing clock detector, and watchdog timer. each reset source is de scribed in the following sections. figure 13.1. reset sources wdt xtal1 xtal2 osc internal clock generator system clock cip-51 microcontroller core missing clock detector (one- shot) wdt strobe software reset extended interrupt handler clock select rst + - v dd supply reset timeout (wired-or) system reset supply monitor pre reset funnel + - cp0+ comparator0 cp0- (port i/o) crossbar cnvstr (cnvstr reset enable) (cp0 reset enable) en wdt enable en mcd enable (wired-or) vdd monitor reset enable c8051f040/1/2/3/4/5/6/7 166 rev. 1.5 13.1. power-on reset the c8051f04x family incorporates a power supply monitor that holds the mcu in the reset state until v dd rises above the v rst level during power-up. see figure 13.2 for timing diagram, and refer to table 13.1 for the electrical characteristics of the power supply monitor circuit. the /rst pin is asserted low until the end of the 100 ms v dd monitor timeout in order to allow the v dd supply to stabilize. the v dd monitor reset is enabled and disabled using the external v dd monitor enable pin (monen). on exit from a power-on reset, the porsf flag (rstsrc. 1) is set by hardware to logic 1. all of the other reset flags in the rstsrc register are indeterminate. porsf is cleared by all other resets. since all resets cause program execution to begin at the same location (0x0000), software can read the porsf flag to determine if a power-up was the cause of reset. the contents of internal data memory should be assumed to be undefined after a power-on reset. figure 13.2. reset timing 13.2. power-fail reset when a power-down transition or power irregularity causes v dd to drop below v rst , the power supply monitor will drive the /rst pin low and return the cip-51 to the reset state. when v dd returns to a level above v rst , the cip-51 will leave the reset state in the sa me manner as that for the power-on reset (see figure 13.2). note that even though internal data me mory contents are not altered by the power-fail reset, it is impossible to determine if v dd dropped below the level required for data retention. if the porsf flag is set to logic 1, the data may no longer be valid. 13.3. external reset the external /rst pin provides a means for external ci rcuitry to force the mcu into a reset state. asserting the /rst pin low will cause the mcu to enter the reset state. it may be des irable to provide an external pul- vdd monitor reset power-on reset /rst t volts 1.0 2.0 logic high logic low reset time delay reset time delay v d d 2.70 2.55 v rst c8051f040/1/2/3/4/5/6/7 rev. 1.5 167 lup and/or decoupling of the /rst pin to avoid erroneous noise-induc ed resets. the mcu will remain in reset until at least 12 clock cycles after the active-low /rst signal is removed. the pinrsf flag (rst- src.0) is set on exit from an external reset. 13.4. missing clock detector reset the missing clock detector is essentia lly a one-shot circuit that is trigger ed by the mcu system clock. if the system clock goes away for more than 100 s, t he one-shot will time out and generate a reset. after a missing clock detector reset, the mcdrsf flag (rst src.2) will be set, signifying the mcd as the reset source; otherwise, this bit reads ?0?. the state of t he /rst pin is unaffected by this reset. setting the mcdrsf bit, rstsrc.2 (see section ? 14. oscillators ? on page 173 ) enables the missing clock detector. 13.5. comparator0 reset comparator0 can be configured as a reset input by writing a ?1? to the c0 rsef flag (rstsrc.5). comparator0 should be enabled using cpt0cn.7 (see section ? 11. comparators ? on page 121 ) prior to writing to c0rsef to prevent any turn-on chatter on the output from generating an unwanted reset. the comparator0 reset is active-low: if the non-invertin g input voltage (cp0+ pin) is less than the inverting input voltage (cp0- pin), the mcu is put into the rese t state. after a comparator0 reset, the c0rsef flag (rstsrc.5) will read ?1? signifying comp arator0 as the reset sour ce; otherwise, this bit reads ?0?. the state of the /rst pin is unaffected by this reset. 13.6. external cnvstr0 pin reset the external cnvstr0 signal can be configured as a reset input by writing a ?1? to the cnvrsef flag (rstsrc.6). the cnvstr0 signal can appear on any of the p0, p1, p2 or p3 i/o pins as described in section ? 17.1. ports 0 through 3 and the priority crossbar decoder ? on page 204 . note that the cross- bar must be configured for the cnvstr0 signal to be routed to the appropriate port i/o. the crossbar should be configured and enabled before the cnvrsef is set. when configured as a reset, cnvstr0 is active-low and level sensitive. after a cnvstr0 re set, the cnvrsef flag (rstsrc.6) will read ?1? signi- fying cnvstr0 as the reset source; otherwise, this bit re ads ?0?. the state of the /rst pin is unaffected by this reset. 13.7. watchdog timer reset the mcu includes a program mable watchdog timer (wdt ) running off the system clock. a wdt overflow will force the mcu into the rese t state. to prevent the reset, the wdt mu st be restarted by application soft- ware before overflow. if the system experiences a soft ware or hardware malfuncti on preventing the soft- ware from restarting the wdt, th e wdt will overflow and cause a rese t. this should pr event the system from running out of control. following a reset the wdt is automatically enabled and running with the default maximum time interval. if desired the wdt can be disabled by system software or locked on to prevent accidental disabling. once locked, the wdt cannot be disabled until the next syst em reset. the state of the /rst pin is unaffected by this reset. the wdt consists of a 21-bit timer running from th e programmed system clock. the timer measures the period between specific writes to its control register. if this period exceeds the programmed limit, a wdt reset is generated. the wdt can be enabled and disabled as needed in software, or can be permanently enabled if desired. watchdog features are contro lled via the watchdog timer control register (wdtcn) shown in sfr definition 13.1. c8051f040/1/2/3/4/5/6/7 168 rev. 1.5 13.7.1. enable/reset wdt the watchdog timer is both enabled and reset by writing 0xa5 to the wdtcn register. the user's applica- tion software should include periodic writes of 0x a5 to wdtcn as needed to prevent a watchdog timer overflow. the wdt is enabled and rese t as a result of any system reset. 13.7.2. disable wdt writing 0xde followed by 0xad to the wdtcn regi ster disables the wdt. the following code segment illustrates disabling the wdt: clr ea ; disable all interrupts mov wdtcn,#0deh ; disable software watchdog timer mov wdtcn,#0adh setb ea ; re-enable interrupts the writes of 0xde and 0xad must occur within 4 clo ck cycles of each other, or the disable operation is ignored. interrupts should be disabled during this procedure to avoid delay between the two writes. 13.7.3. disable wdt lockout writing 0xff to wdtcn locks out the disable feature. once locked out, the disable operation is ignored until the next system reset. writing 0xff does not enabl e or reset the watchdog timer. applications always intending to use the watchdog should writ e 0xff to wdtcn in the initialization code. 13.7.4. setting wdt interval wdtcn.[2:0] control the watchdog timeout interval. the interval is given by the following equation: ; where t sysclk is the system clock period. for a 3 mhz system clock, this provides an interval range of 0.021 ms to 349.5 ms. wdtcn.7 must be logic 0 when setting this interval . reading wdtcn returns the programmed interval. wdtcn.[2:0] reads 111b after a system reset. 4 3 wdtcn 20 ? ?? t sysclk ? c8051f040/1/2/3/4/5/6/7 rev. 1.5 169 sfr definition 13.1. wdtcn: watchdog timer control bits7-0: wdt control writing 0xa5 both enables and reloads the wdt. writing 0xde followed within 4 system clocks by 0xad disables the wdt. writing 0xff locks out the disable feature. bit4: watchdog status bit (when read) reading the wdtcn.[4] bit indicates the watchdog timer status. 0: wdt is inactive 1: wdt is active bits2-0: watchdog timeout interval bits the wdtcn.[2:0] bits set the watchdog timeout interval. when writing these bits, wdtcn.7 must be set to 0. r/wr/wr/wr/wr/wr/wr/w r/wreset value xxxxx111 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: sfr page: 0xff all pages c8051f040/1/2/3/4/5/6/7 170 rev. 1.5 sfr definition 13.2. rstsrc: reset source bit7: reserved. bit6: cnvrsef: convert start reset source enable and flag write: 0: cnvstr0 is not a reset source. 1: cnvstr0 is a reset source (active low). read: 0: source of prior reset was not cnvstr0. 1: source of prior reset was cnvstr0. bit5: c0rsef: comparator0 reset enable and flag. write: 0: comparator0 is not a reset source. 1: comparator0 is a reset source (active low). read: 0: source of last reset was not comparator0. 1: source of last reset was comparator0. bit4: swrsf: software reset force and flag. write: 0: no effect. 1: forces an internal reset. /rst pin is not effected. read: 0: source of last reset was not a write to the swrsf bit. 1: source of last reset was a write to the swrsf bit. bit3: wdtrsf: watchdog timer reset flag. 0: source of last reset was not wdt timeout. 1: source of last reset was wdt timeout. bit2: mcdrsf: missing clock detector flag. write: 0: missing clock detector disabled. 1: missing clock detector enabled; triggers a reset if a missing clock condition is detected. read: 0: source of last reset was not a missing clock detector timeout. 1: source of last reset was a missing clock detector timeout. bit1: porsf: power-on reset flag. write: if the v dd monitor circuitry is enabled (by tying t he monen pin to a logic high state), this bit can be written to select or de-select the v dd monitor as a reset source. 0: de-select the v dd monitor as a reset source. 1: select the v dd monitor as a reset source. important: at power-on, the v dd monitor is enabled/disabled using the external v dd moni- tor enable pin (monen). the porsf bit does not disable or enable the v dd monitor cir- cuit. it simply selects the v dd monitor as a reset source. read: this bit is set whenever a power-on reset occurs. this may be due to a true power-on reset or a v dd monitor reset. in either case, data memory should be considered indeterminate following the reset. 0: source of last reset was not a power-on or v dd monitor reset. 1: source of last reset was a power-on or v dd monitor reset. note: when this flag is read as '1', all other reset flags are indeterminate. bit0: pinrsf: hw pin reset flag. write: 0: no effect. 1: forces a power-on reset. /rst is driven low. read: 0: source of prior reset was not /rst pin. 1: source of prior reset was /rst pin. r r/w r/w r/w r r/w r r/w reset value - cnvrsef c0rsef swrsef wdtrsf mcdrsf porsf pinrsf 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: sfr page: 0xef 0 c8051f040/1/2/3/4/5/6/7 rev. 1.5 171 table 13.1. reset electrical characteristics ?40 to +85 c unless otherwise specified. parameter conditions min typ max units rst output low voltage i ol = 8.5 ma, v dd = 2.7 v to 3.6 v ??0.6 v rst input high voltage 0.7 x v dd ?? v rst input low voltage ?? 0.3 x v dd rst input leakage current rst = 0.0 v ?50? a v dd for /rst output valid 1.0 ? ? v av+ for /rst output valid 1.0 ? ? v v dd por threshold (v rst ) 2.40 2.55 2.70 v minimum /rst low time to generat e a system reset 10 ? ? ns reset time delay rst rising edge after v dd crosses v rst threshold 80 100 120 ms missing clock detector ? timeout time from last system clock to reset initiation 100 220 500 s c8051f040/1/2/3/4/5/6/7 172 rev. 1.5 c8051f040/1/2/3/4/5/6/7 rev. 1.5 173 14. oscillators figure 14.1. oscillator diagram 14.1. programmable internal oscillator all c8051f04x devices include a programmable internal oscillator that defaults as the system clock after a system reset. the internal oscillator period can be programmed via the oscicl register as defined by sfr definition 14.1. oscicl is factory ca librated to obtain a 24.5 mhz frequency. electrical specifications for the prec ision internal oscillator are given in table 14.1 on page 175. the pro- grammed internal oscillator frequency must not exc eed 25 mhz. the system cl ock may be derived from the programmed internal oscilla tor divided by 1, 2, 4, or 8, as defined by the ifcn bits in register oscicn. osc programmable internal clock generator input circuit en sysclk n oscicl oscicn ioscen ifrdy ifcn1 ifcn0 xtal1 xtal2 option 2 vdd xtal1 option 1 option 3 xtal1 xtal2 option 4 xtal1 oscxcn xtlvld xoscmd2 xoscmd1 xoscmd0 xfcn2 xfcn1 xfcn0 clksel clksl 0 1 c8051f040/1/2/3/4/5/6/7 174 rev. 1.5 sfr definition 14.1. oscicl: internal osci llat or calibration sfr definition 14.2. oscicn: internal os cillator control bits 7-0: oscicl: internal os cillator calibration register this register calibrates the internal oscillator period. the reset value for oscicl defines the internal oscillator base frequency. the reset value is factory calibrated to generate an inter- nal oscillator frequency of 24.5 mhz. r/wr/wr/wr/wr/wr/wr/w r/wreset value variable bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: sfr page: 0x8b f bit7: ioscen: internal oscillator enable bit. 0: internal oscillator disabled 1: internal oscillator enabled bit6: ifrdy: internal oscilla tor frequency ready flag. 0: internal oscillator is not running at prog rammed frequency. 1: internal oscillator is r unning at progra mmed frequency. bits5-2: reserved. bits1-0: ifcn1-0: internal osc illator frequency control bits. 00: sysclk derived from intern al oscillator divided by 8. 01: sysclk derived from intern al oscillator divided by 4. 10: sysclk derived from intern al oscillator divided by 2. 11: sysclk derived from internal oscillator divided by 1. r/w r/w r/w r r/w r/w r/w r/w reset value ioscen ifrdy - - - - ifcn1 ifcn0 11000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: sfr page: 0x8a f c8051f040/1/2/3/4/5/6/7 rev. 1.5 175 14.2. external oscill ator drive circuit the external oscillator circuit may drive an external cr ystal, ceramic resona tor, capacitor, or rc network. a cmos clock may also provide a clock input. for a crys tal or ceramic resonator configuration, the crystal/ resonator must be wired across the xtal1 and xtal2 pi ns as shown in option 1 of figure 14.1. in rc, capacitor, or cmos clock configuration, the clock source should be wired to the xtal2 and/or xtal1 pin(s) as shown in option 2, 3, or 4 of figure 14.1. the type of external oscillator must be selected in the oscxcn register, and the frequency control bits (xfcn) must be selected appro priately (see sfr defini- tion 14.4). 14.3. system clock selection the clksl bit in register clksel se lects which oscillator is used as the system clock. clksl must be set to ?1? for the system clock to run from the external oscillator; ho wever the external oscillator may still clock peripherals (timers, pca) when the internal oscillator is selected as the system clock. the system clock may be switched on -the-fly betwe en the internal and exter nal oscillator, so long as the selected oscil- lator is enabled and has settled. the internal oscilla tor requires little start-up ti me and may be enabled and selected as the system clock in the same write to os cicn. external crystals an d ceramic resonators typi- cally require a start-up time before they are settled and ready for use as the system clock. the crystal valid flag (xtlvld in register oscxcn ) is set to ?1? by hardware when t he external oscillator is settled. to avoid reading a false xtlvld in crystal mode, software should delay at least 1 ms between enabling the external oscillator and checking xtlvld. rc and c modes typically require no startup time. sfr definition 14.3. clksel: oscillator clock selection table 14.1. internal oscillator elec trical characteristics ?40 to +85 c unless otherwise specified. parameter conditions min typ max units calibrated internal oscillator ? frequency 24 24.5 25 mhz internal oscillator supply current (fro m v dd ) oscicn.7 = 1 ?450? a external clock frequency 0?30mhz t xch (external clock high time) 15 ? ? ns t xcl (external clock low time) 15 ? ? ns bits7-1: reserved. bit0: clksl: system clo ck source select bit. 0: sysclk derived from the inte rnal oscillator , and scaled as per the ifcn bits in oscicn. 1: sysclk derived from the external oscillator circuit. r r r r r r r r/w reset value -------clksl00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: sfr page: 0x97 f c8051f040/1/2/3/4/5/6/7 176 rev. 1.5 sfr definition 14.4. oscxcn: external oscillator control bit7: xtlvld: crystal oscillator valid flag. ( read only when xoscmd = 11x. ) 0: crystal oscillator is unused or not yet stable. 1: crystal oscillator is running and stable. bits6-4: xoscmd2-0: extern al oscillator mode bits. 00x: external osc illator circuit off. 010: external cmos clock mode (exter nal cmos clock input on xtal1 pin). 011: external cmos clock mode with divide by 2 stage (external cmos clock input on xtal1 pin). 10x: rc/c oscillator mode with divide by 2 stage. 110: crystal oscillator mode. 111: crystal oscillator mode with divide by 2 stage. bit3: reserved. read = 0, write = don't care. bits2-0: xfcn2-0: external osc illator frequency control bits. 000-111: see table below: crystal mode (circuit from figure 14.1 , option 1; xoscmd = 11x) choose xfcn value to match crystal frequency. rc mode (circuit from figure 14.1, option 2; xoscmd = 10x) choose xfcn value to match frequency range: f = 1.23(10 3 ) / (r x c) , where f = frequency of oscillation in mhz c = capacitor value in pf r = pullup resistor value in k ? c mode (circuit from figure 14.1, option 3; xoscmd = 10x) choose k factor (kf) for the oscillation frequency desired: f = kf / (c x v dd ) , where f = frequency of oscillation in mhz c = capacitor value on xtal1, xtal2 pins in pf v dd = power supply on mcu in volts r r/w r/w r/w r r/w r/w r/w reset value xtlvld xoscmd2 xoscmd1 xoscmd 0 - xfcn2 xfcn1 xfcn0 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: sfr page: 0x8c f xfcn crystal (xoscmd = 11x) rc (xoscmd = 10x) c (xoscmd = 10x) 000 f ? 32 khz f ?? 25 khz k factor = 0.87 001 32 khz ?? f ?? 84 khz 25 khz ?? f ?? 50 khz k factor = 2.6 010 84 khz ? f ?? 225 khz 50 khz ?? f ?? 100 khz k factor = 7.7 011 225 khz ? f ?? 590 khz 100 khz ?? f ?? 200 khz k factor = 22 100 590 khz ? f ?? 1.5 mhz 200 khz ?? f ?? 400 khz k factor = 65 101 1.5 mhz ? f ?? 4 mhz 400 khz ?? f ?? 800 khz k factor = 180 110 4 mhz ? f ?? 10 mhz 800 khz ?? f ?? 1.6 mhz k factor = 664 111 10 mhz ? f ?? 30 mhz 1.6 mhz ?? f ?? 3.2 mhz k factor = 1590 c8051f040/1/2/3/4/5/6/7 rev. 1.5 177 14.4. external crystal example if a crystal or ceramic resonator is used as an external oscillator source for the mcu, the circuit should be configured as shown in figure 14.1 , option 1. the external oscillato r frequency contro l value (xfcn) should be chosen from the crystal column of the ta ble in sfr definition 14.4 (oscxcn register). for example, an 11.0592 mhz crystal requires an xfcn setting of 111b. when the crystal oscillator is enabled , the oscillator amplitude detection circuit requires a settle time to achieve proper bias. introducing a delay of at least 1 ms between enabling the oscillator and checking the xtlvld bit will prevent a premature switch to the extern al oscillator as the system clock. switching to the external oscillator before the crysta l oscillator has stabilized can result in unpredictable behavior. the rec- ommended procedure is: step 1. enable the external o scillator in crystal oscillator mode. step 2. wait at least 1 ms. step 3. poll for xtlvld => '1'. step 4. switch the system cl ock to the external oscillator. note: t uning-fork crystals may requir e additional settling time before xtlvld returns a valid result. the capacitors shown in the external crystal configur ation provide the load capacitance required by the crystal for correct oscillation. these capacitors are "in series" as seen by the crystal and "in parallel" with the stray capacitance of the xtal1 and xtal2 pins. note: the load capacitance depends upon the crystal an d the manufacturer. please refer to the crystal data sheet when completing these calculations. for example, a tuning-fork crystal of 32.768 khz wi th a recommended load capacitance of 12.5 pf should use the configuration shown in figure 14.1, option 1. the total value of the capacitors and the stray capac- itance of the xtal pins should equal 25 pf. with a stra y capacitance of 3 pf per pin, the 22 pf capacitors yield an equivalent capacitance of 12.5 pf across the crystal, as shown in figure 14.2. figure 14.2. 32. 768 khz external crystal example important note on external crystals: crystal oscillator circuits are qui te sensitive to pcb layout. the crystal should be placed as close as possible to the xtal pins on the device. the traces should be as short as possible and shielded with ground plane fr om any other traces which could introduce noise or interference. 22 pf 22 pf 32.768 khz xtal1 xtal2 10 m ? c8051f040/1/2/3/4/5/6/7 178 rev. 1.5 14.5. external rc example if an rc network is used as an external oscillator so urce for the mcu, the circ uit should be configured as shown in figure 14.1, option 2. the capacitor should be no greater than 100 pf; however, for very small capacitors, the total capacitance may be dominated by parasitic capacitance in the pcb layout. to deter- mine the required external oscilla tor frequency control va lue (xfcn) in the oscxcn register, first select the rc network value to prod uce the desired frequency of oscilla tion. if the frequency desired is 100 khz, let r = 246 k ? and c = 50 pf: f = 1.23( 10 3 ) / rc = 1.23 ( 10 3 ) / [ 246 x 50 ] = 0.1 mhz = 100 khz referring to the table in sfr definition 14.4 , the required xfcn setting is 010b. 14.6. external capacitor example if a capacitor is used as an external oscillator for t he mcu, the circuit should be configured as shown in figure 14.1, option 3. the capacitor should be no gr eater than 100 pf; however, for very small capacitors, the total capacitance may be dominated by parasiti c capacitance in the pcb layout. to determine the required external oscillato r frequency control value (xfcn) in th e oscxcn register, select the desired frequency of oscillation and find the capacitor to be used from the equations below. assume v dd = 3.0 v and f = 50 khz: f = kf / ( c x v dd ) = kf / ( c x 3 ) = 0.050 mhz if a frequency of roughly 50 khz is desired, select the k factor from the table in sfr definition 14.4 as kf = 7.7: 0.050 mhz = 7.7 / (c x 3) c x 3 = 7.7 / 0.050 = 154, so c = 154 / 3 pf = 51.3 pf therefore, the xfcn value to use in this example is 010b. c8051f040/1/2/3/4/5/6/7 rev. 1.5 179 15. flash memory the c8051f04x family includes 64 kb + 128 (c8051f040/1/2/3/4/5) or 32 kb + 128 (c8051f046/7) of on- chip, reprogrammable flash memory for program code and non-volatile data storage. the flash memory can be programmed in-system, a single byte at a time, through the jtag interface or by software using the movx write instructions. once cleared to logic 0, a flash bit must be erased to set it back to logic 1. the bytes would typically be erased (set to 0xff) bef ore being reprogrammed. flash write and erase opera- tions are automatically timed by hardware for proper execution; data polling to determine the end of the write/erase operation is not required. the cpu is st alled during write/erase operations while the device peripherals remain active. interrupts that occur during flash write/erase operations are held, and are then serviced in their priority order once the flash operatio n has completed. refer to table 15.1 for the electri- cal characteristics of the flash memory. 15.1. programming the flash memory the simplest means of programming the flash memory is through the jtag interface using programming tools provided by silicon labs or a third party vendor. this is the only means for programming a non-initial- ized device. for details on the jtag commands to program flash memory, see section ?25.2. flash pro- gramming commands? on page 321 . the flash memory can be programmed by software using the movx write instru ction with the address and data byte to be programmed provided as normal ope rands. before writing to flash memory using movx, flash write operations must be enabled by setting th e pswe program store write enable bit (psctl.0) to logic 1. this directs the movx writes to flash memory instead of to xr am, which is the default target. the pswe bit remains set until cleared by software. to avoi d errant flash writes, it is recommended that inter- rupts be disabled while the pswe bit is logic 1. flash memory is read using the movc instruction. movx reads are always directed to xram, regardless of the state of pswe. note : to ensure the integrity of flash memory conten ts, it is strongly reco mmended that the on-chip v dd monitor be enabled by connecting the v dd monitor enable pin (monen) to v dd in any system that exe- cutes code that writes and/or erases flash memory from software. see ?reset sources? on page 165 for more information. a write to flash memory can clear bits but cannot set them; only an erase operation can set bits in flash. a byte location to be programmed must be erased before a new value can be written . the flash memory is organized in 512-byte pages. the erase operat ion applies to an entire page (setting all bytes in the page to 0xff). the following steps illustrate the algorithm for prog ramming flash by user software. step 1. disable interrupts. step 2. set flwe (flscl.0) to enable flash writes/erases via user software. step 3. set psee (psctl.1) to enable flash erases. step 4. set pswe (psctl.0) to redire ct movx commands to write to flash. step 5. use the movx command to write a data byte to any location within the 512-byte page to be erased. step 6. clear psee to disable flash erases step 7. use the movx command to write a data by te to the desired byte location within the erased 512-byte page. repeat this step until a ll desired bytes are written (within the target page). step 8. clear the pswe bit to redirect movx commands to the xram data space. step 9. re-enable interrupts. write/erase timing is automatically co ntrolled by hardware. note that code execution in the 8051 is stalled while the flash is being programmed or erased. note that 512 bytes at locations 0xfe00 (c8051f040/1/2/ c8051f040/1/2/3/4/5/6/7 180 rev. 1.5 3/4/5) and all locations above 0x8000 (c8051f046/7) ar e reserved. flash writes and erases targeting the reserved area should be avoided. 15.2. non-volatile data storage the flash memory can be used for non-volatile data storage as well as program code. this allows data such as calibration coefficients to be calculated and stored at run time. data is written using the movx write instruction (as described in the previous section) and read using the movc instruction. an additional 128-byte sector of flash memory is incl uded for non-volatile data storage. its smaller sector size makes it particularly well suit ed as general purpose, non-volatile scratchpad memory. even though flash memory can be written a single byte at a time, an entire sector must be erased first. in order to change a single byte of a multi-byte data set, the data must be moved to temporary storage. the 128-byte sector-size facilitates updating data without wasting program memory or ram space. the 128-byte sector is double-mapped over the 64k byte flash memory; its address ranges from 0x00 to 0x7f (see figure 15.1). to access this 128-byte sector, the sfle bit in psctl must be set to logic 1. code execution from this 128-byte scratchpad sector is not permitted. 15.3. security options the cip-51 provides security options to protect the flash memory from inadvertent modification by soft- ware as well as prevent the viewing of proprietary program code and constants. the program store write enable (psctl.0) and the program store erase enable (psctl.1) bits protect the flash memory from accidental modification by software. these bits must be ex plicitly set to logic 1 befo re software can write or erase the flash memory. additional se curity features prevent proprietary program code and data constants from being read or altered across the jtag interfac e or by software running on the system controller. a set of security lock bytes stored at 0xfdfe and 0xfdff (c8051f040/1/2/3/4/5) and at 0x7ffe and 0x7fff (c8051f046/7) protect the flash program memo ry from being read or altered across the jtag interface. each bit in a security lock-byte protects one 8k-byte block of memory. clearing a bit to logic 0 in a read lock byte prevents the corresponding block of flash memory from being read across the jtag interface. clearing a bit in the writ e/erase lock byte protects the block from jtag erasures and/or writes. the read lock byte is at locations 0xfdff (c8051f 040/1/2/3/4/5) and 0x7fff (c8051f046/7). the write/erase lock byte is located at 0xfdfe (c8051f040/1/2/3/4/5) and 0x7ffe (c8051f046/7). figure 15.1 shows the location and bit definitions of the security bytes. the 512-byte sector containing the lock bytes can be written to, but not erased by software . an attempted read of a read-locked byte returns undefined data. debugging code in a read-locked sector is not possible through the jtag inter- face. table 15.1. flash electrical characteristics v dd = 2.7 to 3.6 v; t a = ?40 to +85 c parameter conditions min typ max units flash size 1 c8051f040/1/2/3/4/5 ? c8051f046/7 65664 2 32896 bytes endurance 20 k 100 k ? erase/write erase cycle time 10 12 14 ms write cycle time 40 50 60 s notes: 1. in cludes 128-byte scratchpad. 2. 512 bytes at locations 0xfe00 to 0xffff are reserved. c8051f040/1/2/3/4/5/6/7 rev. 1.5 181 figure 15.1. flash program memo ry map and security bytes flash read lock byte bits7-0: each bit locks a correspondi ng block of memory. (bit7 is msb). 0: read operations are locked (disabled) fo r corresponding block across the jtag interface. 1: read operations are unlocked (enabled) fo r corresponding block across the jtag inter- face. flash write/erase lock byte bits7-0: each bit locks a corresponding block of memory. 0: write/erase operations are locked (disabled) for corresponding block across the jtag interface. 1: write/erase operations are unlocked (enabled) for corresponding block across the jtag interface. note: when the highest block is locked, the se curity bytes may be written but not erased. flash access limit register (flacl) the content of this register is used as the high byte of the 16-bit software read limit address. this 16-bit read limit address value is calculated as 0xnn00 where nn is replaced by content of this register on reset. software running at or above this address is prohibited from using the movx and movc instructions to read, write, or erase flash locations below this address. any attempts to read locations below this limit will return the value 0x00. 0xfe00 0xfdfe program/data memory space 0x0000 0xfdff read lock byte write/erase lock byte software read limit reserved 0xfdfd sfle = 0 bit memory block c8051f040/1/2/3/4/5 c8051f046/7 7 6 5 4 0xc000 - 0xdfff 0xe000 - 0xfdfd 0xa000 - 0xbfff 0x8000 - 0x9fff 3 2 1 0 0x4000 - 0x5fff 0x6000 - 0x7fff 0x2000 - 0x3fff 0x0000 - 0x1fff read and write/erase security bits. (bit 7 is msb.) 0x007f 0x0000 scratchpad memory (data only) sfle = 1 0x8000 0x7ffe program/data memory space 0x0000 0x7fff read lock byte write/erase lock byte software read limit reserved 0x7ffd c8051f040/1/2/3/4/5 c8051f046/7 no effect no effect no effect no effect 0x4000 - 0x5fff 0x6000 - 0x7ffd 0x2000 - 0x3fff 0x0000 - 0x1fff c8051f040/1/2/3/4/5/6/7 182 rev. 1.5 the lock bits can always be read and cleared to logi c 0 regardless of the security setting applied to the block containing the security bytes. this allows additi onal blocks to be protected after the block containing the security bytes has been locked. important note: the only means of removing a lock once set is to erase the entire program memory space by performing a jtag erase operation (i.e., cannot be done in user firmware). addressing either security byte while performing a jtag erase operation will automatically initiate erasure of the entire program memory space (except for the reserved area). this erasure can only be performed via jt ag. if a non-security byte in the 0xfbff-0xfdff (c8051f040/1/2/3/4/5) or 0x7dff-0x7fff (c8051f046/7) page is addressed during the jtag era- sure, only that page (including the security bytes) will be erased. the flash access limit security feature (see figure 15.1) protects proprietary program code and data from being read by software running on the c8051f04x. th is feature provides suppor t for oems that wish to program the mcu with proprietary value-added firmwa re before distribution. the value-added firmware can be protected while allowing additional code to be programmed in remaining program memory space later. the software read limit (srl) is a 16-bit address that establishes two logical pa rtitions in the program memory space. the first is an upper partition consisti ng of all the program memory locations at or above the srl address, and the second is a lower partition co nsisting of all the program memory locations start- ing at 0x0000 up to (but excluding) the srl address. software in the upper pa rtition can execute code in the lower partition, but is prohibited from reading locations in th e lower partition using the movc instruc- tion. (executing a movc instruction from the upper pa rtition with a source address in the lower partition will always return a data value of 0x00. ) software running in th e lower partition can acce ss locations in both the upper and lower partition without restriction. the value-added firmware should be placed in the lowe r partition. on reset, cont rol is passed to the value- added firmware via the reset vector. once the value- added firmware completes it s initial execution, it branches to a predetermined location in the upper partition. if entry points are published, software running in the upper partition may execute program code in the lower partition, but it cann ot read the contents of the lower partition. parameters may be passed to the program code running in the lower partition either through the typical method of placing them on the stack or in registers before the call or by placing them in prescribed memory locations in the upper partition. the srl address is specified using the contents of th e flash access register. the 16-bit srl address is calculated as 0xnn00, where nn is the contents of the srl security register. thus, the srl can be located on 256-byte boundaries anywhere in program memory space. however, the 512-byte erase sector size essentially requires that a 512 boundary be used. the contents of a non-initialized srl security byte is 0x00, thereby setting the srl add ress to 0x0000 and allowing read access to all locations in program memory space by default. c8051f040/1/2/3/4/5/6/7 rev. 1.5 183 15.3.1. summary of flash security options there are three flash access methods supported on the c8051f04x devices; 1) accessing flash through the jtag debug interface, 2) accessing flash from firmware residing below the flash access limit, and 3) accessing flash from firmware residing at or above the flash access limit. accessing flash through the jtag debug interface: 1. the read and write/erase lock bytes (securit y bytes) provide secu rity for flash access through the jtag interface. 2. any unlocked page may be read from, written to, or erased. 3. locked pages cannot be read from, written to, or erased. 4. reading the security bytes is always permitted. 5. locking additional pages by writing to t he security bytes is always permitted. 6. if the page containing the security bytes is unloc ked , it can be directly erased. doing so will reset the security bytes and unlock all pages of flash. 7. if the page containing the security bytes is loc ked , it cannot be directly erased. to unlock the page containing the security bytes, a full jtag device erase is required. a full jtag device erase will erase all flash pages, includi ng the page containing the security bytes and the security bytes themselves. 8. the reserved area cannot be read from, written to, or erased at any time. accessing flash from firmware residing below the flash access limit: 1. the read and write/erase lock bytes (security by tes) do not restrict flash access from user firmware. 2. any page of flash except the page containing th e security bytes may be read from, written to, or erased. 3. th e page containing the security bytes cannot be erased. unlocking pages of flash can only be performed via the jtag interface. 4. the page containing the security bytes may be re ad from or written to. pages of flash can be locked from jtag access by wr iting to the se curity bytes. 5. the reserved area cannot be read from, written to, or erased at any time. accessing flash from firmware residing at or above the flash access limit: 1. the read and write/erase lock bytes (security by tes) do not restrict flash access from user firmware. 2. any page of flash at or above the flash access lim it except the page containing the security bytes may be read from, written to, or erased. 3. any page of flash below the flash access limit cannot be read from, written to, or erased. 4. code branches to locations below the flash access limit are permitted. 5. th e page containing the security bytes cannot be erased. unlocking pages of flash can only be performed via the jtag interface. 6. the page containing the security bytes may be re ad from or written to. pages of flash can be locked from jtag access by wr iting to the se curity bytes. 7. the reserved area cannot be read from, written to, or erased at any time. c8051f040/1/2/3/4/5/6/7 184 rev. 1.5 sfr definition 15.1. flacl: flash access limit sfr definition 15.2. flscl: flash memory control bits 7-0: flacl: flash access limit. this register holds the high byte of the 16 -bit program memory read/write/erase limit address. the entire 16-bit access limit address value is calculated as 0xnn00 where nn is replaced by contents of flacl. a write to this register sets the flash access limit. this reg- ister can only be written once after any reset. any subsequent writes are ignored until the next reset. r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: sfr address: sfr page: 0xb7 f bit7: fose: flash on e-shot timer enable this is the timer that turns off the sense amps after a flash read. 0: flash one-shot timer disabled. 1: flash one-shot timer enabled (recommended setting). bit6: frae: flash read always enable 0: flash reads occur as necessary (recommended setting). 1: flash reads occur every system clock cycle. bits5-1: reserved. read = 0 0000b. must write 00000b. bit0: flwe: flash write/erase enable this bit must be set to allow flash writes/erases from user software. 0: flash writes/erases disabled. 1: flash writes/erases enabled. r/w r/w r/w r/w r/w r/w r/w r/w reset value fose frae reserved reserved reserved reserved reserved flwe 10000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: sfr address: sfr page: 0xb7 0 c8051f040/1/2/3/4/5/6/7 rev. 1.5 185 sfr definition 15.3. psctl: program store re ad/write control bits7-3: unused. read = 00000b, write = don't care. bit2: sfle: scratchpad flash memory access enable when this bit is set, flash reads and writes from user software are directed to the 128-byte scratchpad flash sector. when sfle is set to logic 1, flash accesses out of the address range 0x00-0x7f should not be attempted. reads/writes out of this ra nge will yield unde- fined results. 0: flash access from user software directed to the program/data flash sector. 1: flash access from user software directed to the 128 byte scratchpad sector. bit1: psee: program store erase enable. setting this bit allows an entire page of th e flash program memory to be erased provided the pswe bit is also set. afte r setting this bit, a write to flash memory using the movx instruction will erase the entire page that contains the loca tion addressed by the movx instruction. the value of the data byte written does not matter. note: the flash page con- taining the read lock byte and write/erase lock bytes cannot be erased by soft- ware. 0: flash program memory erasure disabled. 1: flash program memory erasure enabled. bit0: pswe: program store write enable. setting this bit allows writing a byte of dat a to the flash program memory using the movx write instruction. the location must be erased prior to writing data. 0: write to flash program memory disabled. movx write operations target external ram. 1: write to flash program memory enabled. movx write operations target flash memory. r/w r/w r/w r/w r/w r/w r/w r/w reset value - - - - - sfle psee pswe 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: sfr address: sfr page: 0x8f 0 c8051f040/1/2/3/4/5/6/7 186 rev. 1.5 c8051f040/1/2/3/4/5/6/7 rev. 1.5 187 16. external data memory in terface and on-chip xram the c8051f04x mcus include 4 kb of on-chip ram mapped into the external data memory space (xram), as well as an external data memory inte rface which can be used to access off-chip memories and memory-mapped devices connected to the gpio ports. the external memory space may be accessed using the external move instruction (movx) and th e data pointer (dptr), or using the movx indirect addressing mode using r0 or r1. if the movx instru ction is used with an 8-bit address operand (such as @r1), then the high byte of the 16-bit address is pr ovided by the external memory interface control reg- ister (emi0cn, shown in sfr definition 16.1). note : the movx instruction can also be used for writing to the flash memory. see section ?15. flash memory? on page 179 for details. the movx instruction accesses xram by default. the emif can be configured to appear on the lower gpio ports (p0-p3) or the upper gpio ports (p4-p7). 16.1. accessing xram the xram memory space is accessed using the mo vx instruction. the movx instruction has two forms, both of which use an indirect addressing method. th e first method uses the data pointer, dptr, a 16-bit register which contains the effective address of the xram location to be read from or written to. the sec- ond method uses r0 or r1 in combination with the emi0cn register to generate the effective xram address. examples of both of these methods are given below. 16.1.1. 16-bit movx example the 16-bit form of the movx instructi on accesses the memory location po inted to by the contents of the dptr register. the following series of instructions reads the value of the byte at address 0x1234 into the accumulator a: mov dptr, #1234h ; load dptr with 16-bit address to read (0x1234) movx a, @dptr ; load contents of 0x1234 into accumulator a ? the above example uses the 16-bit immediate mov instruction to set th e contents of dptr. alternately, the dptr can be accessed through the sfr registers dph, which contains the upper 8-bits of dptr, and dpl, which contains the lower 8-bits of dptr. 16.1.2. 8-bit movx example the 8-bit form of the movx instruction uses the content s of the emi0cn sfr to determine the upper 8-bits of the effective address to be accessed and the contents of r0 or r1 to determine the lower 8-bits of the effective address to be accessed. the following series of instructions read the contents of the byte at address 0x1234 into the accumulator a. mov emi0cn, #12h ; load high byte of address into emi0cn mov r0, #34h ; load low byte of address into r0 (or r1) movx a, @r0 ; load contents of 0x1234 into accumulator a c8051f040/1/2/3/4/5/6/7 188 rev. 1.5 16.2. configuring the external memory interface configuring the external memory interface consists of five steps: 1. select emif on low ports (p3, p2, p1, and p0) or high ports (p7, p6, p5, and p4). 2. configure the output modes of the port pins as either push-pull or open-drain. 3. select multiplexed mode o r non-multiplexed mode. 4. select the memory mode (on-chip only, split mode without bank select, split mode with bank selec t, or off-chip only). 5. set up timing to interface with off-chip memory or peripherals. ? each of these five steps is explained in detail in the following s ections. the po rt selection, multiplexed mode selection, and mode bits are located in the emi0cf register shown in sfr definition 16.2. 16.3. port selection and configuration the external memory interface can appear on ports 3, 2, 1, and 0 (c8051f04x devices) or on ports 7, 6, 5, and 4 (c8051f040/2/4/6 devices only), depending on the state of the prtsel bit (emi0cf.5). if the lower ports are selected, the emifle bit (xbr2.1) must be set to a ?1? so that the crossbar will skip over p0.7 (/wr), p0.6 (/rd), and, if mult iplexed mode is selected, p0.5 (ale). for more information about the configuring the crossbar, see section ?17.1. ports 0 through 3 and the priority crossbar decoder? on page 204 . the external memory interface claims the associated port pins for memory oper ations only during the execution of an off-chip movx instruction. once the movx instruction has completed, control of the port pins reverts to the port latches or to t he crossbar (on ports 3, 2, 1, and 0). see section ?17. port input/ output? on page 203 for more information about the crossbar and port operation and configuration. the port latches should be ex plicitly configured as pu sh-pull to ?park? the external memory interface pins in a dormant state, most comm only by setting them to a logic 1 . during the execution of the movx instruction, the external memory interf ace will explicitly disable the driv- ers on all port pins that are acting as inputs (data[ 7:0] during a read operation , for example). the output mode of the port pins (whether the pin is configured as open-drain or push-pull) is unaffected by the external memory interface operation, and remains cont rolled by the pnmdout registers. in most cases, the output modes of all emif pins should be configured for push-pull mode. see section ?17.1.2. configuring the output modes of the port pins? on page 206 . c8051f040/1/2/3/4/5/6/7 rev. 1.5 189 sfr definition 16.1. emi0cn: external memo ry interface control bits7-0: pgsel[7:0]: xr am page select bits. the xram page select bits provide the high byte of the 16-bit external data memory address when using an 8-bit movx command, effectively selecting a 256-byte page of ram. 0x00: 0x0000 to 0x00ff 0x01: 0x0100 to 0x01ff ... 0xfe: 0xfe00 to 0xfeff 0xff: 0xff00 to 0xffff r/w r/w r/w r/w r/w r/w r/w r/w reset value pgsel7 pgsel6 pgsel5 pgsel4 pgsel 3 pgsel2 pgsel1 pgsel0 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: sfr page: 0xa2 0 c8051f040/1/2/3/4/5/6/7 190 rev. 1.5 sfr definition 16.2. emi0cf: external memory configuration bits7-6: unused. read = 00b. write = don?t care. bit5: prtsel: emif port select. 0: emif active on p0-p3. 1: emif active on p4-p7. bit4: emd2: emif multiplex mode select. 0: emif operates in multiplexed address/data mode. 1: emif operates in non-multiplexed mode (separate address and data pins). bits3-2: emd1-0: emif op erating mode select. these bits control the operating mode of the external memory interface. 00: internal only: movx accesses on-chip xram only. all effective addresses alias to on- chip memory space. 01: split mode without bank select: accesses below the 4k boundary are directed on-chip. accesses above the 4k boundary are directed off-chip. 8-bit off-chip movx operations use the current contents of the address high port latches to resolve upper address byte. note that in order to access off-chip space, emi0cn must be set to a page that is not contained in the on-chip address space. 10: split mode with bank select: accesses be low the 4k boundary are directed on-chip. accesses above the 4k boundary are directed off-chip. 8-bit off-chip movx operations use the contents of emi0cn to dete rmine the high-byte of the address. 11: external only: movx accesses off-chip xram only. on-chip xram is not visible to the cpu. bits1-0: eale1-0: ale pulse-wi dth select bits (only has effect when emd2 = 1). 00: ale high and ale low pulse width = 1 sysclk cycle. 01: ale high and ale low pulse width = 2 sysclk cycles. 10: ale high and ale low pulse width = 3 sysclk cycles. 11: ale high and ale low pulse width = 4 sysclk cycles. r/w r/w r/w r/w r/w r/w r/w r/w reset value - - prtsel emd2 emd1 emd0 eale1 eale0 00000011 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: sfr page: 0xa3 0 c8051f040/1/2/3/4/5/6/7 rev. 1.5 191 16.4. multiplexed and non-multiplexed selection the external memory interface is capable of acting in a multiplexe d mode or a non-multiplexed mode, depending on the state of the emd2 (emi0cf.4) bit. 16.4.1. multiplexed configuration in multiplexed mode, the data bus and the lower 8-bits of the address bus share the same port pins: ad[7:0]. in this mode , an external latch (74hc373 or equivalent logic gate) is used to hold the lower 8-bits of the ram address. the external latch is controlled by the ale (address latch enable) signal, which is driven by the external memory interface logic. an example of a multiplexed configuration is shown in figure 16.1. in multiplexed mode, the external movx operation can be broken into two phases delineated by the state of the ale signal. during the first phase, ale is high and the lower 8-bits of the address bus are pre- sented to ad[7:0]. during this phase , the address latch is configured such that the ?q? outputs reflect the states of the ?d? inputs. when ale falls, signaling th e beginning of the second phase, the address latch outputs remain fixed and are no longer dependent on the latch inputs. later in the second phase, the data bus controls the state of the ad[7:0] port at the time /rd or /wr is asserted. see section ?16.6.2. multiplexed mode? on page 199 for more information. figure 16.1. multiplexed configuration example address/data bus address bus e m i f a[15:8] ad[7:0] /wr /rd ale 64k x 8 sram oe we i/o[7:0] 74hc373 g dq a[15:8] a[7:0] ce v dd 8 (optional) c8051f040/1/2/3/4/5/6/7 192 rev. 1.5 16.4.2. non-multiplexed configuration in non-multiplexed mode, the data bus and the addr ess bus pins are not shared. an example of a non- multiplexed configuration is shown in figure 16.2. see section ?16.6.1. non-multiplexed mode? on page 196 for more information about non-multiplexed operation. figure 16.2. non-multiplexed configuration example address bus e m i f a[15:0] 64k x 8 sram a[15:0] data bus d[7:0] i/o[7:0] v dd 8 /wr /rd oe we ce (optional) c8051f040/1/2/3/4/5/6/7 rev. 1.5 193 16.5. memory mode selection the external data memory space can be configured in one of four modes, shown in figure 16.3, based on the emif mode bits in the emi0cf register (sfr definition 16.2). these modes are summarized below. more information about the different modes can be found in section ?16.6. timing? on page 194 . 16.5.1. internal xram only when emi0cf.[3:2] are set to ?00?, all movx instructions will ta rget the internal xram space on the device. memory accesses to addres ses beyond the populated space will wrap on 4k bound aries. as an example, the addresses 0x1000 and 0x2000 both evaluate to address 0x0000 in on-chip xram space. ? 8-bit movx operations use the contents of emi0cn to determine the high-byte of the effective address and r0 or r1 to determine the lo w-byte of the effective address. ? 16-bit movx operations use the contents of the 16-bit dptr to determine the effective address. 16.5.2. split mode without bank select when emi0cf.[3:2] are set to ?01?, the xram memory map is split into two areas, on-chip space and off- chip space. ? effective addresses below the 4k bo undary will access on-chip xram space. ? effective addresses above the 4k boundary will access off-chip space. ? 8-bit movx operations use the contents of emi0 cn to determine whether the memory access is on- chip or off-chip. however, in th e ?no bank select? mode, an 8-bi t movx operation will not drive the upper 8-bits a[15:8] of the address bus during an off-chip access. this allows the user to manipulate the upper address bits at will by setting the port state directly via the port latc hes. this behavior is in contrast with ?split mode with bank select? described below. the lower 8-bits of the address bus a[7:0] are driven, determined by r0 or r1. ? 16-bit movx operations use the contents of dptr to determine whether the memory access is on- chip or off-chip, and unlike 8-bit movx operations, the full 16-bits of the address bus a[15:0] are driven during the off-chip transaction. figure 16.3. emif operating modes emi0cf[3:2] = 00 0xffff 0x0000 emi0cf[3:2] = 11 0xffff 0x0000 emi0cf[3:2] = 01 0xffff 0x0000 emi0cf[3:2] = 10 on-chip xram on-chip xram on-chip xram on-chip xram on-chip xram on-chip xram off-chip memory (no bank select) on-chip xram 0xffff 0x0000 off-chip memory (bank select) on-chip xram off-chip memory c8051f040/1/2/3/4/5/6/7 194 rev. 1.5 16.5.3. split mode with bank select when emi0cf.[3:2] are set to ?10?, the xram memory map is split into two areas, on-chip space and off- chip space. ? effective addresses below the 4k bo undary will access on-chip xram space. ? effective addresses above the 4k boundary will access off-chip space. ? 8-bit movx operations use the contents of emi0 cn to determine whether the memory access is on- chip or off-chip. the upper 8-bits of the address bus a[15:8] are determined by emi0cn, and the lower 8-bits of the address bus a[7:0] are determined by r0 or r1. all 16-bits of the address bus a[15:0] are driven in ?bank select? mode. ? 16-bit movx operations use the contents of dptr to determine whether the memory access is on- chip or off-chip, and the full 16-bits of the address bus a[15:0] are driven during the off-chip transac- tion. 16.5.4. external only when emi0cf[3:2] are set to ?11?, all movx operations are directed to off-chip space. on-chip xram is not visible to the cpu. this mode is useful for ac cessing off-chip memory located between 0x0000 and the 4k boundary. ? 8-bit movx operations ignore the contents of emi0 cn. the upper address bits a[15:8] are not driven (identical behavior to an off-chip access in ?split mode without bank select? described above). this allows the user to manipulate the upp er address bits at will by setting the port state directly. the lower 8-bits of the effective address a[7:0] are determined by the contents of r0 or r1. ? 16-bit movx operations use the contents of dptr to determine the effective address a[15:0]. the full 16-bits of the address bus a[15:0] are driven during the off-chip transaction. 16.6. timing the timing parameters of the external memory inte rface can be configured to enable connection to devices having different setup and hold time requirements. the address setup time, address hold time, / rd and ? /wr strobe widths, and in multiplexed mode, the width of the ale pulse are all programmable in units of sysclk periods through emi0tc, shown in sfr definition 16.3, and emi0cf[1:0]. the timing for an off-chip movx instruction can be calculated by adding 4 sysclk cycles to the timing parameters defined by the emi0tc register. assumi ng non-multiplexed operation, the minimum execution time for an off-chip xram operat ion is 5 sysclk cycles (1 sysclk for /rd or /wr pulse + 4 sysclks). for multiplexed operations , the address latch enable signal will re quire a minimum of 2 additional sys- clk cycles. therefore, the minimum ex ecution time of an off-chip xram operation in multiplexed mode is 7 sysclk cycles (2 sysclks for /ale, 1 for /rd or /wr + 4 sysclks). the programmable setup and hold times default to the maximu m delay settings after a reset. table 16.1 lists the ac parameters for the external memory interface, and figure 16.4 through figure 16.9 show the timing diagrams for the different exte rnal memory interface modes and movx operations. c8051f040/1/2/3/4/5/6/7 rev. 1.5 195 sfr definition 16.3. emi0tc: external me mory t iming control bits7-6: eas1-0: emif address setup time bits. 00: address setup time = 0 sysclk cycles. 01: address setup time = 1 sysclk cycle. 10: address setup time = 2 sysclk cycles. 11: address setup time = 3 sysclk cycles. bits5-2: ewr3-0: emif /wr and /rd pulse-width control bits. 0000: /wr and /rd pulse width = 1 sysclk cycle. 0001: /wr and /rd pulse width = 2 sysclk cycles. 0010: /wr and /rd pulse width = 3 sysclk cycles. 0011: /wr and /rd pulse width = 4 sysclk cycles. 0100: /wr and /rd pulse width = 5 sysclk cycles. 0101: /wr and /rd pulse width = 6 sysclk cycles. 0110: /wr and /rd pulse width = 7 sysclk cycles. 0111: /wr and /rd pulse width = 8 sysclk cycles. 1000: /wr and /rd pulse width = 9 sysclk cycles. 1001: /wr and /rd pulse wid th = 10 sysclk cycles. 1010: /wr and /rd pulse width = 11 sysclk cycles. 1011: /wr and /rd pulse width = 12 sysclk cycles. 1100: /wr and /rd pulse width = 13 sysclk cycles. 1101: /wr and /rd pulse width = 14 sysclk cycles. 1110: /wr and /rd pulse width = 15 sysclk cycles. 1111: /wr and /rd pulse width = 16 sysclk cycles. bits1-0: eah1-0: emif address hold time bits. 00: address hold time = 0 sysclk cycles. 01: address hold time = 1 sysclk cycle. 10: address hold time = 2 sysclk cycles. 11: address hold time = 3 sysclk cycles. r/w r/w r/w r/w r/w r/w r/w r/w reset value eas1 eas0 erw3 ewr2 ewr1 ewr0 eah1 eah0 11111111 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: sfr page: 0xa1 0 c8051f040/1/2/3/4/5/6/7 196 rev. 1.5 16.6.1. non-multiplexed mode 16.6.1.1.16-bit movx: emi0cf[4:2] = ?101?, ?110?, or ?111?. figure 16.4. non-multip lexed 16-bit movx timing emif address (8 msbs) from dph emif address (8 lsbs) from dpl p2/p6 p1/p5 p0.7/p4.7 p0.6/p4.6 p3/p7 emif write data p2/p6 p1/p5 p0.7/p4.7 p0.6/p4.6 p3/p7 t ach t wdh t acw t acs t wds addr[15:8] addr[7:0] data[7:0] /wr /rd emif address (8 msbs) from dph emif address (8 lsbs) from dpl p2/p6 p1/p5 p0.6/p4.6 p0.7/p4.7 p3/p7 p2/p6 p1/p5 p0.6/p4.6 p0.7/p4.7 p3/p7 t ach t rdh t acw t acs t rds addr[15:8] addr[7:0] data[7:0] /rd /wr emif read data nonmuxed 16-bit write nonmuxed 16-bit read c8051f040/1/2/3/4/5/6/7 rev. 1.5 197 16.6.1.2.8-bit movx without bank select: emi0cf[4:2] = ?101? or ?111?. figure 16.5. non-multip lexed 8-bit movx withou t bank select timing emif address (8 lsbs) from r0 or r1 p2/p6 p1/p5 p0.7/p4.7 p0.6/p4.6 p3/p7 emif write data p2/p6 p0.7/p4.7 p0.6/p4.6 p3/p7 t ach t wdh t acw t acs t wds addr[15:8] addr[7:0] data[7:0] /wr /rd emif address (8 lsbs) from r0 or r1 p2/p6 p1/p5 p0.6/p4.6 p0.7/p4.7 p3/p7 p2/p6 p0.6/p4.6 p0.7/p4.7 p3/p7 t ach t rdh t acw t acs t rds addr[15:8] addr[7:0] data[7:0] /rd /wr emif read data nonmuxed 8-bit write without bank select nonmuxed 8-bit read without bank select c8051f040/1/2/3/4/5/6/7 198 rev. 1.5 16.6.1.3.8-bit movx with bank select: emi0cf[4:2] = ?110?. figure 16.6. non-multip lexed 8-bit movx with bank select timing emif address (8 msbs) from emi0cn emif address (8 lsbs) from r0 or r1 p2/p6 p1/p5 p0.7/p4.7 p0.6/p4.6 p3/p7 emif write data p2/p6 p1/p5 p0.7/p4.7 p0.6/p4.6 p3/p7 t ach t wdh t acw t acs t wds addr[15:8] addr[7:0] data[7:0] /wr /rd emif address (8 msbs) from emi0cn emif address (8 lsbs) from r0 or r1 p2/p6 p1/p5 p0.6/p4.6 p0.7/p4.7 p3/p7 p2/p6 p1/p5 p0.6/p4.6 p0.7/p4.7 p3/p7 t ach t rdh t acw t acs t rds addr[15:8] addr[7:0] data[7:0] /rd /wr emif read data nonmuxed 8-bit write with bank select nonmuxed 8-bit read with bank select c8051f040/1/2/3/4/5/6/7 rev. 1.5 199 16.6.2. multiplexed mode 16.6.2.1.16-bit movx: emi0cf[4:2] = ?001 ?, ?010?, or ?011?. figure 16.7. multiple xed 16-bit movx timing p3/p7 p2/p6 p3/p7 addr[15:8] ad[7:0] p2/p6 p0.7/p4.7 p0.6/p4.6 p0.5/p4.5 p0.7/p4.7 p0.6/p4.6 p0.5/p4.5 t ach t wdh t acw t acs t wds ale /wr /rd emif address (8 msbs) from dph emif write data emif address (8 lsbs) from dpl t aleh t alel p3/p7 p2/p6 p3/p7 addr[15:8] ad[7:0] p2/p6 p0.6/p4.6 p0.7/p4.7 p0.5/p4.5 p0.6/p4.6 p0.7/p4.7 p0.5/p4.5 t ach t acw t acs ale /rd /wr emif address (8 msbs) from dph emif address (8 lsbs) from dpl t aleh t alel t rdh t rds emif read data muxed 16-bit write muxed 16-bit read c8051f040/1/2/3/4/5/6/7 200 rev. 1.5 16.6.2.2.8-bit movx without bank select: emi0cf[4:2] = ?001? or ?011?. figure 16.8. multiplexed 8-bit mo vx without bank select timing p3/p7 p2/p6 p3/p7 addr[15:8] ad[7:0] p0.7/p4.7 p0.6/p4.6 p0.5/p4.5 p0.7/p4.7 p0.6/p4.6 p0.5/p4.5 t ach t wdh t acw t acs t wds ale /wr /rd emif write data emif address (8 lsbs) from r0 or r1 t aleh t alel p3/p7 p2/p6 p3/p7 addr[15:8] ad[7:0] p0.6/p4.6 p0.7/p4.7 p0.5/p4.5 p0.6/p4.6 p0.7/p4.7 p0.5/p4.5 t ach t acw t acs ale /rd /wr emif address (8 lsbs) from r0 or r1 t aleh t alel t rdh t rds emif read data muxed 8-bit write without bank select muxed 8-bit read without bank select c8051f040/1/2/3/4/5/6/7 rev. 1.5 201 16.6.2.3.8-bit movx with bank select: emi0cf[4:2] = ?010?. figure 16.9. multiplexed 8-bit movx with bank select timing p3/p7 p2/p6 p3/p7 addr[15:8] ad[7:0] p2/p6 p0.7/p4.7 p0.6/p4.6 p0.5/p4.5 p0.7/p4.7 p0.6/p4.6 p0.5/p4.5 t ach t wdh t acw t acs t wds ale /wr /rd emif address (8 msbs) from emi0cn emif write data emif address (8 lsbs) from r0 or r1 t aleh t alel p3/p7 p2/p6 p3/p7 addr[15:8] ad[7:0] p2/p6 p0.6/p4.6 p0.7/p4.7 p0.5/p4.5 p0.6/p4.6 p0.7/p4.7 p0.5/p4.5 t ach t acw t acs ale /rd /wr emif address (8 msbs) from emi0cn emif address (8 lsbs) from r0 or r1 t aleh t alel t rdh t rds emif read data muxed 8-bit write with bank select muxed 8-bit read with bank select c8051f040/1/2/3/4/5/6/7 202 rev. 1.5 table 16.1. ac parameters for extern al memory interface parameter description min max units t sysclk system clock period 40 ? ns t acs address/control setup time 0 3 x t sysclk ns t acw address/control pulse width 1 x t sysclk 16 x t sysclk ns t ach address/control hold time 0 3 x t sysclk ns t aleh address latch enable high time 1 x t sysclk 4 x t sysclk ns t alel address latch enable low time 1 x t sysclk 4 x t sysclk ns t wds write data setup time 1 x t sysclk 19 x t sysclk ns t wdh write data hold time 0 3 x t sysclk ns t rds read data setup time 20 ? ns t rdh read data hold time 0?n s c8051f040/1/2/3/4/5/6/7 rev. 1.5 203 17. port input/output the c8051f04x family of devices are fully integrated mixed-signal system on a chip mcus with 64 digital i/o pins (c8051f040/2/4/6) or 32 digital i/o pins (c80 51f041/3/5/7), organized as 8-bit ports. all ports are both bit- and byte-addressable throu gh their corresponding port data regi sters. all port pins are 5 v-toler- ant, and all support configurable open-drain or push-pull output modes and weak pullups. a block dia- gram of the port i/o cell is shown in figure 17.1. comp lete electrical specificatio ns for the port i/o pins are given in table 17.1. figure 17.1. port i/o cell block diagram table 17.1. port i/o dc electri cal characteristics v dd = 2.7 to 3.6 v, ?40 to +85 c unless otherwise specified. parameter conditions min typ max units output high voltage (v oh ) i oh = ?3 ma, port i/o push-pull i oh = ?10 a, port i/o push-pull i oh = ?10 ma, port i/o push-pull v dd ? 0.7 v dd ? 0.1 ? ? ? v dd ? 0.8 ? ? ? v output low voltage (v ol ) i ol = 8.5 ma i ol = 10 a i ol = 25 ma ? ? ? ? ? 1.0 0.6 0.1 ? v input high voltage (vih) 0.7 x v dd ?? input low voltage (vil) ? ? 0.3 x v dd input leakage current dgnd < port pin < v dd , pin tri-state weak pullup off weak pullup on ? ? ? ? ? 10 ? 1 ? a input capacitance ?5?pf dgnd /port-outenable port-output push-pull vdd vdd /weak-pullup (weak) port pad analog input analog select (ports 1, 2, and 3) port-input c8051f040/1/2/3/4/5/6/7 204 rev. 1.5 the c8051f04x family of devices hav e a wide array of digital resources which are available through the four lower i/o ports: p0, p1, p2, and p3. each of the pins on p0, p1, p2, and p3, can be defined as a gen- eral-purpose i/o (gpio) pin or can be controlled by a digital peripheral or function (like uart0 or /int1 for example), as shown in figure 17.2. the system designer controls which digital functions are assigned pins, limited only by the number of pins available. this resource assignment flexibility is achieved through the use of a priority crossbar decoder. the state of a port i/o pin can always be read from its associated data register regardless of whether that pin has been assigned to a digital peripheral or behaves as gpio. the port pins on ports 1, 2, and 3 can be used as an alog inputs to adc2 (c8051 f040/1/2/3 on ly), analog voltage comparators, and adc0, respectively. figure 17.2. port i/o fun ctional block diagram an external memory interface, which is active during the execution of an off-chip movx instruction, can be active on either the lower ports or the upper ports. see section ?16. external data memory interface and on-chip xram? on page 187 for more information about the external memory interface. 17.1. ports 0 through 3 and the priority crossbar decoder the priority crossbar decoder, or ?crossbar?, allocate s and assigns port pins on port 0 through port 3 to the digital peripherals (uarts, smbus, pca, timers, etc.) on the device using a priority order. the port pins are allocated in order starting with p0.0 and continue through p3.7, if necessary. the digital peripher- als are assigned port pins in a priority order which is listed in figure 17.3, with uart0 having the highest priority and cnvstr2 having the lowest priority. external pins digital crossbar priority decoder smbus 2 spi 4 uart0 2 pca 2 t0, t1, t2, t2ex, t3, t3ex, t4,t4ex, /int0, /int1 p1.0 p1.7 p2.0 p2.7 p0.0 p0.7 highest priority lowest priority 8 8 comptr. outputs (internal digital signals) highest priority lowest priority uart1 6 2 p3.0 p3.7 8 8 p0mdout, p1mdout, p2mdout, p3mdout registers xbr0, xbr1, xbr2, xbr3 p1mdin, p2mdin, p3mdin registers p1 i/o cells p3 i/o cells p0 i/o cells p2 i/o cells 8 port latches p0 p1 p2 8 8 8 p3 8 (p2.0-p2.7) (p1.0-p1.7) (p0.0-p0.7) (p3.0-p3.7) to adc2 input to external memory interface (emif) to adc0 input to comparators /sysclk cnvstr0 cnvstr2 c8051f040/1/2/3/4/5/6/7 rev. 1.5 205 figure 17.3. priority cr ossbar decode table (emifle = 0; p1mdin = 0xff) 17.1.1. crossbar pin assignment and allocation the crossbar assigns port pins to a peripheral if the corresponding enable bits of the peripheral are set to a logic 1 in the crossbar configuration registers xb r0, xbr1, xbr2, and xbr3, shown in sfr definition 17.1, sfr definition 17.2, sfr definition 17.3, and sf r definition 17.4. for example, if the uart0en bit (xbr0.2) is set to a logic 1, the tx0 and rx0 pins will be mapped to p0.0 and p0.1 respectively. because uart0 has the highest priority, its pins will always be mapped to p0.0 and p0.1 when uart0en is set to a logic 1. if a digital peripheral?s enable bits are not set to a logic 1, then its ports are not accessible at the port pins of the device. also note that the crossbar assigns pins to all associated functions when a serial communication peripheral is selected (i.e. smbus, spi, uart). it would be impossible, for example, to assign tx0 to a port pin without assigning rx0 as well. each combination of enabled peripherals results in a unique device pinout. all port pins on ports 0 through 3 that are not allocated by the crossbar can be accessed as general-pur- pose i/o (gpio) pins by reading and writing the associated port data registers (see sfr definition 17.5, pin i/o 01234567012345670123456701234567 tx0 rx0 sck miso mosi nss nss is not assigned to a port pin when the spi is placed in 3-wire mode sda scl tx1 rx1 cex0 cex1 cex2 cex3 cex4 cex5 eci eci0e: xbr0.6 cp0 cp0e: xbr0.7 cp1 cp1e: xbr1.0 cp2 cp2e: xbr3.3 t0 t0e: xbr1.1 /int0 int0e: xbr1.2 t1 t1e: xbr1.3 /int1 int1e: xbr1.4 t2 t2e: xbr1.5 t2ex t2exe: xbr1.6 t3 t3e: xbr3.0 t3ex t3exe: xbr3.1 t4 t4e: xbr2.3 t4ex t4exe: xbr2.4 /sysclk syscke: xbr1.7 cnvstr0 cnvste0: xbr2.0 cnvstr2 cnvste2: xbr3.2 ale /rd /wr ain1.0/a8 ain1.1/a9 ain1.2/a10 ain1.3/a11 ain1.4/a12 ain1.5/a13 ain1.6/a14 ain1.7/a15 a8m/a0 a9m/a1 a10m/a2 a11m/a3 a12m/a4 a13m/a5 a14m/a6 a15m/a7 ad0/d0 ad1/d1 ad2/d2 ad3/d3 ad4/d4 ad5/d5 ad6/d6 ad7/d7 xbr2.2 xbr0.[5:3] uart0en: spi0en: crossbar register bits xbr0.2 xbr0.1 xbr0.0 smb0en: ain1 inputs/non-muxed addr h muxed addr h/non-muxed addr l muxed data/non-muxed data uart1en: pca0me: p0 p1 p2 p3 c8051f040/1/2/3/4/5/6/7 206 rev. 1.5 sfr definition 17.7, sfr definition 17.10, and sfr defi nition 17.13), a set of sfrs which are both byte- and bit-addressable. the output states of port pins th at are allocated by the crossbar are controlled by the digital peripheral that is mapped to those pins. writes to the port data registers (or associated port bits) will have no effect on the states of these pins. a read of a port data register (or port bit) will always return the logic st ate present at the pin itself, regard- less of whether the crossbar has allocated the pin for peripheral use or not. an exception to this occurs during the execution of a read-modify-write instruction (anl, orl, xrl, cpl, inc, dec, djnz, jbc, clr, set, and the bitwise mov operation). during the read cycle of the read-modify-write instruction, it is the contents of the port data register, not the st ate of the port pins themselves, which is read. because the crossbar registers affect the pinout of the peripherals of the device, they are typically config- ured in the initialization code of th e system before the peripherals themselves are configured. once config- ured, the crossbar registers are typically left alone. once the crossbar registers have been properly co nfigured, the crossbar is enabled by setting xbare (xbr2.4) to a logic 1. until xbare is set to a logic 1, the output drivers on ports 0 through 3 are explicitly disabled in order to prevent possible contention on the port pins while the crossbar reg- isters and other registers which can affect the device pinout are being written . the output drivers on crossbar-assigned input signals ( like rx0, for example) are explicitly disabled; thus the values of the port data registers and the pnmd out registers have no effect on the states of these pins. 17.1.2. configuring the output modes of the port pins the output drivers on ports 0 through 3 remain disabl ed until the crossbar is enabled by setting xbare (xbr2.4) to a logic 1. the output mode of each port pin can be configured to be either open-drain or push-pull. in the push-pull configuration, writing a logic 0 to the associated bit in the port data register will cause the port pin to be driven to gnd, and writin g a logic 1 will cause the port pin to be driven to v dd . in the open-drain configu- ration, writing a logic 0 to th e associated bit in the port data register will cause the port pin to be driven to gnd, and a logic 1 will cause the port pin to assume a high-impedance state. the open-drain configura- tion is useful to prevent contention between devices in systems wher e the port pin participates in a shared interconnection in which multiple ou tputs are connected to the same phys ical wire (like the sda signal on an smbus connection). the output modes of the port pins on ports 0 through 3 are determined by the bits in the associated pnmdout registers (see sfr definition 17.6, sfr defi nition 17.9, sfr definition 17.12, and sfr defini- tion 17.15). for example, a logic 1 in p3mdout.7 will configure the output mode of p3.7 to push-pull; a logic 0 in p3mdout.7 will configure the output mode of p3.7 to open-drain. all po rt pins def ault to open- drain output. the pnmdout registers control the out put modes of the port pins regardless of whether the crossbar has allocated the port pin for a digital peripheral or not. the exceptions to this rule are: the port pins connected to sda, scl, rx0 (if uart0 is in mode 0), and rx1 (if uart1 is in mode 0) are always configured as open-drain outputs, regardless of the settings of the associated bits in the pnmdout registers. 17.1.3. configuring port pins as digital inputs a port pin is configured as a digital input by setti ng its output mode to ?open-drain? in the pnmdout reg- ister and writing a logic 1 to the associated bit in the port data register. for example, p3.7 is configured as c8051f040/1/2/3/4/5/6/7 rev. 1.5 207 a digital input by setting p3mdout.7 to a logic 0, wh ich selects open-drain output mode, and p3.7 to a logic 1, which disables the low-side output driver. if the port pin has been assigned to a digital peripheral by the crossbar and that pin functions as an input (for example rx0, the uart0 receive pin), then the ou tput drivers on that pin are automatically disabled. 17.1.4. weak pullups by default, each port pin has an internal weak pullu p device enabled which provides a resistive connection (about 100 k ? ) between the pin and v dd . the weak pullup devices can be globally disabled by writing a logic 1 to the weak pullup disable bit, (weakpud, xbr2 .7). the weak pullup is automatically deactivated on any pin that is driving a logic 0; that is, an output pin will not co ntend with its own pullup device. the weak pullup device can also be explicitly disabled on ports 1, 2, and 3 pin by configuring the pin as an analog input, as described below. 17.1.5. configuring port 1, 2, and 3 pins as analog inputs the pins on port 1 can serve as analog inputs to the adc2 analog mux (c8051 f040/1/2/3 only), the pins on port 2 can serve as analog inputs to the comparator s, and the pins on port 3 can serve as inputs to adc0. a port pin is configured as an analog input by writing a logic 0 to the associated bit in the pnmdin registers. all port pins default to a digital input mode. configuring a port pin as an analog input: 1. disables the digital input path from the pin. th is prevents additional power supply current from being drawn when the voltage at the pin is near v dd / 2. a read of the port dat a bit will return a logic 0 regardless of the voltage at the port pin. 2. disables the weak pullup device on the pin. 3. causes the crossbar to ?skip over? the pin when allocating port pins for digital peripherals. ? note that the output drivers on a pin configured as an analog input are not explic itly disabled. therefore, the associated pnmdout bits of pins configured as analog inputs should explicitly be set to logic 0 (open-drain output mode), and the as sociated port data bits should be set to logic 1 (high-impedance). also note that it is not required to configure a port pin as an analog input in order to use it as an input to the adc?s or comparators; however, it is strongly recommended. see t he analog peripheral?s correspond- ing section in this datash eet for further information. c8051f040/1/2/3/4/5/6/7 208 rev. 1.5 17.1.6. external memory interface pin assignments if the external memory interface (emif) is enabled on the low ports (ports 0 through 3), emifle (xbr2.5) should be set to a logic 1 so that the crossbar will not assign peripherals to p0.7 (/wr ), p0.6 (/rd), and, if the external memory interface is in multiplexed mode, p0.5 (ale). figure 17.4 shows an example cross- bar decode table with emifle=1 and the emif in multiplexed mode. figure 17.5 shows an example crossbar decode table with emifle=1 and the emif in non-multiplexed mode. if the external memory interface is enabled on the low ports and an off-chip movx operation occurs, the external memory in terface will control the output states (logic 1 or logic 0) of the affect ed port pins during the execution phase of the movx inst ruction, regardless of the settings of the crossbar registers or the port data registers. the output configuration (push-pull or open-drain) of the port pins is not affected by the emif operation, except that read operations will explicitly disable the output drivers on the data bus. in most cases, gpio pins used in emif operations (especially the /wr and /rd lines) should be configured as push-pull and ?parked? at a logic 1 state. see section ?16. external data memory interface and on-chip xram? on page 187 for more information about th e external memory interface. figure 17.4. priority cr ossbar decode table (emifle = 1; emif in mult iplexed mode; p1mdin = 0xf f) pin i/o 01234567012345670123456701234567 tx0 rx0 sck miso mosi nss nss is not assigned to a port pin when the spi is placed in 3-wire mode sda scl tx1 rx1 cex0 cex1 cex2 cex3 cex4 cex5 eci eci0e: xbr0.6 cp0 cp0e: xbr0.7 cp1 cp1e: xbr1.0 cp2 cp2e: xbr3.3 t0 t0e: xbr1.1 /int0 int0e: xbr1.2 t1 t1e: xbr1.3 /int1 int1e: xbr1.4 t2 t2e: xbr1.5 t2ex t2exe: xbr1.6 t3 t3e: xbr3.0 t3ex t3exe: xbr3.1 t4 t4e: xbr2.3 t4ex t4exe: xbr2.4 /sysclk syscke: xbr1.7 cnvstr0 cnvste0: xbr2.0 cnvstr2 cnvste2: xbr3.2 ale /rd /wr ain1.0/a8 ain1.1/a9 ain1.2/a10 ain1.3/a11 ain1.4/a12 ain1.5/a13 ain1.6/a14 ain1.7/a15 a8m/a0 a9m/a1 a10m/a2 a11m/a3 a12m/a4 a13m/a5 a14m/a6 a15m/a7 ad0/d0 ad1/d1 ad2/d2 ad3/d3 ad4/d4 ad5/d5 ad6/d6 ad7/d7 xbr2.2 xbr0.[5:3] uart0en: spi0en: crossbar register bits xbr0.2 xbr0.1 xbr0.0 smb0en: ain1 inputs/non-muxed addr h muxed addr h/non-muxed addr l muxed data/non-muxed data uart1en: pca0me: p0 p1 p2 p3 c8051f040/1/2/3/4/5/6/7 rev. 1.5 209 figure 17.5. priority cr ossbar decode table (emifle = 1; emif in non-mu ltiplexed mode; p1mdin = 0xff) pin i/o 01234567012345670123456701234567 tx0 rx0 sck miso mosi nss nss is not assigned to a port pin when the spi is placed in 3-wire mode sda scl tx1 rx1 cex0 cex1 cex2 cex3 cex4 cex5 eci eci0e: xbr0.6 cp0 cp0e: xbr0.7 cp1 cp1e: xbr1.0 cp2 cp2e: xbr3.3 t0 t0e: xbr1.1 /int0 int0e: xbr1.2 t1 t1e: xbr1.3 /int1 int1e: xbr1.4 t2 t2e: xbr1.5 t2ex t2exe: xbr1.6 t3 t3e: xbr3.0 t3ex t3exe: xbr3.1 t4 t4e: xbr2.3 t4ex t4exe: xbr2.4 /sysclk syscke: xbr1.7 cnvstr0 cnvste0: xbr2.0 cnvstr2 cnvste2: xbr3.2 ale /rd /wr ain1.0/a8 ain1.1/a9 ain1.2/a10 ain1.3/a11 ain1.4/a12 ain1.5/a13 ain1.6/a14 ain1.7/a15 a8m/a0 a9m/a1 a10m/a2 a11m/a3 a12m/a4 a13m/a5 a14m/a6 a15m/a7 ad0/d0 ad1/d1 ad2/d2 ad3/d3 ad4/d4 ad5/d5 ad6/d6 ad7/d7 xbr2.2 xbr0.[5:3] uart0en: spi0en: crossbar register bits xbr0.2 xbr0.1 xbr0.0 smb0en: ain1 inputs/non-muxed addr h muxed addr h/non-muxed addr l muxed data/non-muxed data uart1en: pca0me: p0 p1 p2 p3 c8051f040/1/2/3/4/5/6/7 210 rev. 1.5 17.1.7. crossbar pin assignment example in this example (figure 17.6), we configure the crossb ar to allocate port pins for uart0, the smbus, uart1, /int0, and /int1 (8 pins total). additionally, we configure the external memory interface to oper- ate in multiplexed mode and to appear on the low ports. further, we configure p1.2, p1.3, and p1.4 for analog input mode so that the voltages at these pins can be measured by adc2. the configuration steps are as follows: 1. xbr0, xbr1, and xbr2 are set such that uart 0en = 1, smb0en = 1, int0e = 1, int1e = 1, and emifle = 1. thus: xbr0 = 0x05, xbr1 = 0x14, and xbr2 = 0x02. 2. we configure the external memory interface to use multiplexed mode and to appear on the lo w ports. prtsel = 0, emd2 = 0. 3. we configure the desired port 1 pins to analog input mode by se tting p1mdin to 0xe3 (p1.4, p1.3, and p1.2 are analog inputs, so their associated p1mdin bits are set to logic 0). 4. we enable the crossbar by setting xbare = 1: xbr2 = 0x42. - uart0 has the highest priority, so p0.0 is assigned to tx0, and p0.1 is assigned to rx0. - the smbus is next in priority order, so p0.2 is assigned to sda, and p0.3 is assigned to scl. - uart1 is next in priority order, so p0.4 is assigne d to tx1. because the external memory interface is selected on the lower ports, emif le = 1, which causes the crossbar to skip p0.6 (/rd) and p0.7 (/wr). be cause the external memory interface is configured in multi - plexed mode, the crossbar will als o skip p0.5 (ale). rx1 is assigned to the next non- skipped pin, which in this case is p1.0. - /int0 is next in priority order, so it is assigned to p1.1. - p1mdin is set to 0xe3, which configures p1 .2, p1.3, and p1.4 as analog inputs, causing the crossbar to skip these pins. - /int1 is next in priority order, so it is assi gn ed to the next non-skipped pin, which is p1.5. - the external memory interface will drive ports 2 and 3 (denoted by red dots in figure 17.6 ) during the execution of an off-chip movx instruction. 5. we set the uart0 tx pin (tx0, p0.0) and uart1 tx pin (tx1, p0.4) outputs to push-pull by setting p0md out = 0x11. 6. we configure all emif-controlled pins to push-pull output mode by setting p0mdout |= 0xe0; p2mdout = 0xff; p3mdout = 0xff. 7. we explicitly disable th e output drivers on the 3 analog input pins by setting p1mdout = 0 x00 (configure outputs to open-drain) and p1 = 0xff (a logic 1 selects the high-impedance st ate). c8051f040/1/2/3/4/5/6/7 rev. 1.5 211 figure 17.6. crossbar example: (emifle = 1; emif in mult iplexed mode; p1mdin = 0xe3; xbr0 = 0x05; xbr1 = 0x14; xbr2 = 0x42) pin i/o 01234567012345670123456701234567 tx0 rx0 sck miso mosi nss sda scl tx1 rx1 cex0 cex1 cex2 cex3 cex4 cex5 eci eci0e: xbr0.6 cp0 cp0e: xbr0.7 cp1 cp1e: xbr1.0 cp2 cp2e: xbr3.2 t0 t0e: xbr1.1 /int0 int0e: xbr1.2 t1 t1e: xbr1.3 /int1 int1e: xbr1.4 t2 t2e: xbr1.5 t2ex t2exe: xbr1.6 t3 t3e: xbr3.0 t3ex t3exe: xbr3.1 t4 t4e: xbr2.3 t4ex t4exe: xbr2.4 /sysclk syscke: xbr1.7 cnvstr0 cnvste0: xbr2.0 cnvstr2 cnvste2: xbr3.2 ale /rd /wr ain1.0/a8 ain1.1/a9 ain1.2/a10 ain1.3/a11 ain1.4/a12 ain1.5/a13 ain1.6/a14 ain1.7/a15 a8m/a0 a9m/a1 a10m/a2 a11m/a3 a12m/a4 a13m/a5 a14m/a6 a15m/a7 ad0/d0 ad1/d1 ad2/d2 ad3/d3 ad4/d4 ad5/d5 ad6/d6 ad7/d7 xbr2.2 xbr0.[5:3] uart0en: spi0en: crossbar register bits xbr0.2 xbr0.1 xbr0.0 smb0en: ain1 inputs/non-muxed addr h muxed addr h/non-muxed addr l muxed data/non-muxed data uart1en: pca0me: p0 p1 p2 p3 c8051f040/1/2/3/4/5/6/7 212 rev. 1.5 sfr definition 17.1. xbr0: port i/o cro ssb ar register 0 bit7: cp0e: comparator 0 output enable bit. 0: cp0 unavailable at port pin. 1: cp0 routed to port pin. bit6: eci0e: pca0 external counter input enable bit. 0: pca0 external counter in put unavailable at port pin. 1: pca0 external co unter input (eci0) r outed to port pin. bits5-3: pca0me: pca0 mo dule i/o enable bits. 000: all pca0 i/o unavailable at port pins. 001: cex0 routed to port pin. 010: cex0, cex1 routed to 2 port pins. 011: cex0, cex1, and cex2 routed to 3 port pins. 100: cex0, cex1, cex2, and c ex3 routed to 4 port pins. 101: cex0, cex1, cex2, cex3, and cex4 routed to 5 port pins. 110: cex0, cex1, cex2, cex3, cex4, and cex5 routed to 6 port pins. bit2: uart0en: uart0 i/o enable bit. 0: uart0 i/o unavailable at port pins. 1: uart0 tx routed to p0.0 , and rx routed to p0.1. bit1: spi0en: spi0 bus i/o enable bit. 0: spi0 i/o unavailable at port pins. 1: spi0 sck, miso, mosi, and nss routed to 4 port pins. note that the nss signal is not assigned to a port pin if the spi is in 3-wire mode. see section ? 20. enhanced serial peripheral interface (spi0) ? on page 255 for more information. bit0: smb0en: smbus0 bus i/o enable bit. 0: smbus0 i/o unavailable at port pins. 1: smbus0 sda and scl routed to 2 port pins. r/w r/w r/w r/w r/w r/w r/w r/w reset value cp0e eci0e pca0me uart0en spi0en smb0en 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: sfr page: 0xe1 f c8051f040/1/2/3/4/5/6/7 rev. 1.5 213 sfr definition 17.2. xbr1: port i/o cro ssb ar register 1 bit7: syscke: /sysclk output enable bit. 0: /sysclk unavailable at port pin. 1: /sysclk routed to port pin. bit6: t2exe: t2ex input enable bit. 0: t2ex unavailable at port pin. 1: t2ex routed to port pin. bit5: t2e: t2 input enable bit. 0: t2 unavailable at port pin. 1: t2 routed to port pin. bit4: int1e: /int1 input enable bit. 0: /int1 unavailable at port pin. 1: /int1 routed to port pin. bit3: t1e: t1 input enable bit. 0: t1 unavailable at port pin. 1: t1 routed to port pin. bit2: int0e: /int0 input enable bit. 0: /int0 unavailable at port pin. 1: /int0 routed to port pin. bit1: t0e: t0 input enable bit. 0: t0 unavailable at port pin. 1: t0 routed to port pin. bit0: cp1e: cp1 output enable bit. 0: cp1 unavailable at port pin. 1: cp1 routed to port pin. r/w r/w r/w r/w r/w r/w r/w r/w reset value syscke t2exe t2e int1e t1e int0e t0e cp1e 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: sfr page: 0xe2 f c8051f040/1/2/3/4/5/6/7 214 rev. 1.5 sfr definition 17.3. xbr2: port i/o cro ssb ar register 2 bit7: weakpud: weak pullup disable bit. 0: weak pullups globally enabled. 1: weak pullups globally disabled. bit6: xbare: crossb ar enable bit. 0: crossbar disabled. all pins on ports 0, 1, 2, and 3, are forced to input mode. 1: crossbar enabled. bit5: unused. read = 0, write = don't care. bit4: t4exe: t4ex input enable bit. 0: t4ex unavailable at port pin. 1: t4ex routed to port pin. bit3: t4e: t4 input enable bit. 0: t4 unavailable at port pin. 1: t4 routed to port pin. bit2: uart1e: uart1 i/o enable bit. 0: uart1 i/o unavailable at port pins. 1: uart1 tx and rx routed to 2 port pins. bit1: emifle: external memory interface low-port enable bit. 0: p0.7, p0.6, and p0.5 functions are determ ined by the crossbar or the port latches. 1: if emi0cf.4 = ?0? (external memory interface is in multiplexed mode) p0.7 (/wr), p0.6 (/rd), and p0.5 (ale) are ?skipped? by the crossbar and their out- put states are determined by the port latches and the external memory interface. 1: if emi0cf.4 = ?1? (external memory interface is in no n-multiplexed mode) p0.7 (/wr) and p0.6 (/rd) are ?skipped? by the crossbar and their output states are determined by the port latches and the external memory interface. bit0: cnvst0e: adc0 external convert start input enable bit. 0: cnvst0 for adc0 unavailable at port pin. 1: cnvst0 for adc0 r outed to port pin. r/w r/w r/w r/w r/w r/w r/w r/w reset value weakpud xbare ? t4exe t4e uart1e emifle cnvst0e 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: sfr page: 0xe3 f c8051f040/1/2/3/4/5/6/7 rev. 1.5 215 sfr definition 17.4. xbr3: port i/o cro ssb ar register 3 sfr definition 17.5. p0: port0 data bit7: ctxout: can transmit pin (ctx) output mode. 0: ctx pin output mode is configured as open-drain. 1: ctx pin output mode is configured as push-pull. bit6-4: reserved bit3: cp2e: cp2 output enable bit. 0: cp2 unavailable at port pin. 1: cp2 routed to port pin. bit2: cnvst2e: adc2 external convert start input enable bit (c8051f040/1/2/3 only). 0: cnvst2 for adc2 unavailable at port pin. 1: cnvst2 for adc2 r outed to port pin. bit1: t3exe: t3ex input enable bit. 0: t3ex unavailable at port pin. 1: t3ex routed to port pin. bit0: t3e: t3 input enable bit. 0: t3 unavailable at port pin. 1: t3 routed to port pin. r/w r r r r/w r/w r/w r/w reset value ctxout ? ? ? cp2e cnvst2e t3exe t3e 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: sfr page: 0xe4 f bits7-0: p0.[7:0]: port0 output latch bits. (write - output appears on i/o pins per xbr0, xbr1, xbr2, and xbr3 registers) 0: logic low output. 1: logic high output (open if corresponding p0mdout.n bit = 0). (read - regardless of xbr0, xbr1, xbr2, and xbr3 register settings). 0: p0.n pin is logic low. 1: p0.n pin is logic high. note: p0.7 (/wr), p0.6 (/rd), and p0.5 (ale) can be driven by the external data memory interface. see section ?16. external data memory interface and on-chip xram? on page 187 for more information. see also sfr defini tion 17.3 for information about configur- ing the crossbar for ex ternal memory accesses. r/w r/w r/w r/w r/w r/w r/w r/w reset value p0.7 p0.6 p0.5 p0.4 p0.3 p0.2 p0.1 p0.0 11111111 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 bit addressable sfr address: sfr page: 0x80 all pages c8051f040/1/2/3/4/5/6/7 216 rev. 1.5 sfr definition 17.6. p0mdout: port0 output mode sfr definition 17.7. p1: port1 data bits7-0: p0mdout.[7:0]: port0 output mode bits. 0: port pin output mode is configured as open-drain. 1: port pin output mode is configured as push-pull. note: sda, scl, and rx0 (when uart0 is in mode 0) and rx1 (when uart1 is in mode 0) are always configured as open-drain when they appear on port pins. r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: sfr page: 0xa4 f bits7-0: p1.[7:0]: port1 output latch bits. (write - output appears on i/o pins per xbr0, xbr1, xbr2, and xbr3 registers) 0: logic low output. 1: logic high output (open if corresponding p1mdout.n bit = 0). (read - regardless of xbr0, xbr1, xbr2, and xbr3 register settings). 0: p1.n pin is logic low. 1: p1.n pin is logic high. notes: 1. p1.[7:0] can be configured as inputs to adc1 as ain1.[7:0], in which ca se they are ?skipped? by the crossbar assignment process and their digital input paths are disabled, depending on p1mdin (see sfr definition 17.8 ) . note that in analog mode, t he output mode of the pin is determined by the port 1 latch and p1mdout (sfr definition 17.9). see section ?7. 8-bit adc (adc2, c8051f040/1/2/3 only)? on page 91 for more information about adc2. 2. p1.[7:0] can be driven by the external data memory interface (as address[15:8] in non-mul- tiplexed mode). see section ?16. external data memory interface and on-chip xram? on page 187 for more information about the external memory interface. r/w r/w r/w r/w r/w r/w r/w r/w reset value p1.7 p1.6 p1.5 p1.4 p1.3 p1.2 p1.1 p1.0 11111111 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 bit addressable sfr address: sfr page: 0x90 all pages c8051f040/1/2/3/4/5/6/7 rev. 1.5 217 sfr definition 17.8. p1mdin: port1 input mode sfr definition 17.9. p1mdout: port1 output mode bits7-0: p1mdin.[7:0]: port 1 input mode bits. 0: port pin is configured in analog input mode. th e digital input path is disabled (a read from the port bit will always retu rn ?0?). the weak pullup on the pin is disabled. 1: port pin is configured in digital input mode. a read from the port bit will return the logic level at the pin. the state of the weak pullup is determined by the weakpud bit (xbr2.7, see sfr definition 17.3). r/w r/w r/w r/w r/w r/w r/w r/w reset value 11111111 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: sfr page: 0xad f bits7-0: p1mdout.[7:0]: port1 output mode bits. 0: port pin output mode is configured as open-drain. 1: port pin output mode is configured as push-pull. note: sda, scl, and rx0 (when uart0 is in mode 0) and rx1 (when uart1 is in mode 0) are always configured as open-drain when they appear on port pins. r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: sfr page: 0xa5 f c8051f040/1/2/3/4/5/6/7 218 rev. 1.5 sfr definition 17.10. p2: port2 data sfr definition 17.11. p2mdin: port2 input mode bits7-0: p2.[7:0]: port2 output latch bits. (write - output appears on i/o pins per xbr0, xbr1, xbr2, and xbr3 registers) 0: logic low output. 1: logic high output (open if corresponding p2mdout.n bit = 0). (read - regardless of xbr0, xbr1, xbr2, and xbr3 register settings). 0: p2.n pin is logic low. 1: p2.n pin is logic high. note: p2.[7:0] can be driven by the external data memory interf ace (as address[15:8] in multi- plexed mode, or as address[7:0] in non-multiplexed mode). see section ?16. external data memory interface and on-chip xram? on page 187 for more information about the external memory interface. r/w r/w r/w r/w r/w r/w r/w r/w reset value p2.7 p2.6 p2.5 p2.4 p2.3 p2.2 p2.1 p2.0 11111111 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 bit addessable sfr address: sfr page: 0xa0 all pages bits7-0: p1mdin.[7:0]: port 2 input mode bits. 0: port pin is configured in analog input mode. th e digital input path is disabled (a read from the port bit will always retu rn ?0?). the weak pullup on the pin is disabled. 1: port pin is configured in digital input mode. a read from the port bit will return the logic level at the pin. the state of the weak pullup is determined by the weakpud bit (xbr2.7, see sfr definition 17.3). r/w r/w r/w r/w r/w r/w r/w r/w reset value 11111111 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: sfr page: 0xae f c8051f040/1/2/3/4/5/6/7 rev. 1.5 219 sfr definition 17.12. p2mdout: port2 output mode sfr definition 17.13. p3: port3 data bits7-0: p2mdout.[7:0]: port2 output mode bits. 0: port pin output mode is configured as open-drain. 1: port pin output mode is configured as push-pull. note: sda, scl, and rx0 (when uart0 is in mode 0) and rx1 (when uart1 is in mode 0) are always configured as open-drain when they appear on port pins. r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: sfr page: 0xa6 f bits7-0: p3.[7:0]: port3 output latch bits. (write - output appears on i/o pins per xbr0, xbr1, xbr2, and xbr3 registers) 0: logic low output. 1: logic high output (open if corresponding p3mdout.n bit = 0). (read - regardless of xbr0, xbr1, xbr2, and xbr3 register settings). 0: p3.n pin is logic low. 1: p3.n pin is logic high. note: p3.[7:0] can be driven by the external data memory interf ace (as ad[7:0] in multiplexed mode, or as d[7:0] in non-multiplexed mode). see section ?16. external data memory interface and on-chip xram? on page 187 for more information about the external mem- ory interface. r/w r/w r/w r/w r/w r/w r/w r/w reset value p3.7 p3.6 p3.5 p3.4 p3.3 p3.2 p3.1 p3.0 11111111 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 bit addressable sfr address: sfr page: 0xb0 all pages c8051f040/1/2/3/4/5/6/7 220 rev. 1.5 sfr definition 17.14. p3mdin: port3 input mode sfr definition 17.15. p3mdout: port3 output mode 17.2. ports 4 through 7 on c8051f040/2/4/6 devices, all po rt pins on ports 4 through 7 can be accessed as general-purpose i/o (gpio) pins by reading and writing the associated po rt data registers (see sfr definition 17.16, sfr definition 17.18, sfr definition 17 .20, and sfr definition 17.22 located on sfr page f ), a set of sfrs which are both bit and byte-addressable. a read of a port data register (or port bit) will always return the logic st ate present at the pin itself, regard- less of whether the crossbar has allocated the pin for peripheral use or not. an exception to this occurs during the execution of a read-modify-write instruction (anl, orl, xrl, cpl, inc, dec, djnz, jbc, clr, set, and the bitwise mov operation). during the read cycle of the read-modify-write instruction, it is the contents of the port data register, not the st ate of the port pins themselves, which is read. bits7-0: p1mdin.[7:0]: port 3 input mode bits. 0: port pin is configured in analog input mode. th e digital input path is disabled (a read from the port bit will always retu rn ?0?). the weak pullup on the pin is disabled. 1: port pin is configured in digital input mode. a read from the port bit will return the logic level at the pin. the state of the weak pullup is determined by the weakpud bit (xbr2.7, see sfr definition 17.3). r/w r/w r/w r/w r/w r/w r/w r/w reset value 11111111 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: sfr page: 0xaf f bits7-0: p2mdout.[7:0]: port3 output mode bits. 0: port pin output mode is configured as open-drain. 1: port pin output mode is configured as push-pull. r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: sfr page: 0xa7 f c8051f040/1/2/3/4/5/6/7 rev. 1.5 221 17.2.1. configuring ports which are not pinned out although p4, p5, p6, and p7 are not brought out to pins on the c8051f041/3/5/7 devices, the port data registers are still pres ent and can be used by software. because th e digital input paths also remain active, it is recommended that these pins not be left in a ?flo ating? state in order to avoid unnecessary power dissi- pation arising from the inputs floating to non-valid logic levels. this condition can be prevented by any of the following: 1. leave the weak pullup devices enabled by setting weakpud (xbr2.7) to a logic 0. 2. configure the output modes of p4, p5, p6, and p7 to ?push-pull? by writing pnout = 0xff. 3. force the output states of p4, p5, p6, and p7 to logic 0 by writing zeros to the port data regis - ters: p4 = 0x00, p5 = 0x00, p6= 0x00, and p7 = 0x00. 17.2.2. configuring the output modes of the port pins the output mode of each port pin can be configured to be either open-drain or push-pull. in the push-pull configuration, a logic 0 in the associ ated bit in the port data register will cause the port pin to be driven to gnd, and a logic 1 will cause the port pin to be driven to v dd . in the open-drain configuration, a logic 0 in the associated bit in the po rt data register will cause the port pi n to be driven to gnd, and a logic 1 will cause the port pin to assume a high-impedance state. the open-drain configuration is useful to prevent contention between devices in syst ems where the port pin participates in a shared interconnection in which multiple outputs are connected to the same physical wire. the output modes of the port pins on ports 4 through 7 are determined by the bits in their respective ? pnmdout output mode registers. ea ch bit in pnmdout controls the output mode of its corresponding port pin (see sfr definition 17.17, sfr definition 17.19, sfr definition 17.21, and sfr definition 17.23). for example, to place port pin 4.3 in push-pull mode (digital output), set p4mdout.3 to logic 1. all port pins default to open-drain mode upon device reset. 17.2.3. configuring port pins as digital inputs a port pin is configured as a digital input by settin g its output mode to "open-drain" in the pnmdout reg- ister and writing a logic 1 to the associated bit in the port data register. for example, p7.7 is configured as a digital input by setting p7mdout.7 to a logic 0, which selects open-drain output mode, and p3.7 to a logic 1, which disables the low-side output driver. 17.2.4. weak pullups by default, each port pin has an internal weak pullu p device enabled which provides a resistive connection (about 100 k ? ) between the pin and v dd . the weak pullup devices can be globally disabled by writing a logic 1 to the weak pullup disable bit, (weakpud, xbr2 .7). the weak pullup is automatically deactivated on any pin that is driving a logic 0; that is, an output pin will not contend wi th its own pullup device. 17.2.5. external memory interface if the external memory interface (e mif) is enabled on the high ports (ports 4 through 7), emifle (xbr2.5) should be set to a logic 0. if the external memory interface is enabled on the high ports and an off-chip movx operation occurs, the external memory interface will contro l the output states of the affected port pins during the execution phase of the movx instruction, regard less of the settings of the port da ta registers. the output configura- tion of the port pins is not affected by the emif oper ation, except that read operations will explicitly dis- able the output drivers on the data bus during the movx execution. see section ?16. external data memory interface and on-chip xram? on page 187 for more information ab out the external memory interface. c8051f040/1/2/3/4/5/6/7 222 rev. 1.5 sfr definition 17.16. p4: port4 data sfr definition 17.17. p4mdout: port4 output mode bits7-0: p4.[7:0]: port4 output latch bits. write - output appears on i/o pins. 0: logic low output. 1: logic high output (open-drain if corresponding p4mdout.n bit = 0). see sfr definition 17.17. read - returns states of i/o pins. 0: p4.n pin is logic low. 1: p4.n pin is logic high. note: p4.7 (/wr), p4.6 (/rd), and p4.5 (ale) can be driven by the external data memory interface. see section ?16. external data memory interface and on-chip xram? on page 187 for more information. r/w r/w r/w r/w r/w r/w r/w r/w reset value p4.7 p4.6 p4.5 p4.4 p4.3 p4.2 p4.1 p4.0 11111111 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 bit addressable sfr address: sfr page: 0xc8 f bits7-0: p4mdout.[7:0]: port4 output mode bits. 0: port pin output mode is configured as open-drain. 1: port pin output mode is configured as push-pull. r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: sfr page: 0x9c f c8051f040/1/2/3/4/5/6/7 rev. 1.5 223 sfr definition 17.18. p5: port5 data sfr definition 17.19. p5mdout: port5 output mode bits7-0: p5.[7:0]: port5 output latch bits. write - output appears on i/o pins. 0: logic low output. 1: logic high output (open-drain if corresponding p5mdout bit = 0). see sfr definition 17.19. read - returns states of i/o pins. 0: p5.n pin is logic low. 1: p5.n pin is logic high. note: p5.[7:0] can be driven by the external data memory interface (as address[15:8] in non-mul- tiplexed mode). see section ?16. external data memory interface and on-chip xram? on page 187 for more information about the external memory interface. r/w r/w r/w r/w r/w r/w r/w r/w reset value p5.7 p5.6 p5.5 p5.4 p5.3 p5.2 p5.1 p5.0 11111111 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 bit addressable sfr address: sfr page: 0xd8 f bits7-0: p5mdout.[7:0]: port5 output mode bits. 0: port pin output mode is configured as open-drain. 1: port pin output mode is configured as push-pull. r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: sfr page: 0x9d f c8051f040/1/2/3/4/5/6/7 224 rev. 1.5 sfr definition 17.20. p6: port6 data sfr definition 17.21. p6mdout: port6 output mode bits7-0: p6.[7:0]: port6 output latch bits. write - output appears on i/o pins. 0: logic low output. 1: logic high output (open-drain if corresponding p6mdout bit = 0). see sfr definition 17.21. read - returns states of i/o pins. 0: p6.n pin is logic low. 1: p6.n pin is logic high. note: p6.[7:0] can be driven by the external data memory interf ace (as address[15:8] in multi- plexed mode, or as address[7:0] in non-multiplexed mode). see section ?16. external data memory interface and on-chip xram? on page 187 for more information about the external memory interface. r/w r/w r/w r/w r/w r/w r/w r/w reset value p6.7 p6.6 p6.5 p6.4 p6.3 p6.2 p6.1 p6.0 11111111 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 bit addressable sfr address: sfr page: 0xe8 f bits7-0: p6mdout.[7:0]: port6 output mode bits. 0: port pin output mode is configured as open-drain. 1: port pin output mode is configured as push-pull. r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: sfr page: 0x9e f c8051f040/1/2/3/4/5/6/7 rev. 1.5 225 sfr definition 17.22. p7: port7 data sfr definition 17.23. p7mdout: port7 output mode bits7-0: p7.[7:0]: port7 output latch bits. write - output appears on i/o pins. 0: logic low output. 1: logic high output (open-drain if corresponding p7mdout bit = 0). see sfr definition 17.23. read - returns states of i/o pins. 0: p7.n pin is logic low. 1: p7.n pin is logic high. note: p7.[7:0] can be driven by the external data memory interf ace (as ad[7:0] in multiplexed mode, or as d[7:0] in non-multiplexed mode). see section ?16. external data memory interface and on-chip xram? on page 187 for more information about the external mem- ory interface. r/w r/w r/w r/w r/w r/w r/w r/w reset value p7.7 p7.6 p7.5 p7.4 p7.3 p7.2 p7.1 p7.0 11111111 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 bit addressable sfr address: sfr page: 0xf8 f bits7-0: p7mdout.[7:0]: port7 output mode bits. 0: port pin output mode is configured as open-drain. 1: port pin output mode is configured as push-pull. note: sda, scl, and rx0 (when uart0 is in mode 0) and rx1 (when uart1 is in mode 0) are always configured as open-drain when they appear on port pins. r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: sfr page: 0x9f f c8051f040/1/2/3/4/5/6/7 226 rev. 1.5 c8051f040/1/2/3/4/5/6/7 rev. 1.5 227 18. controller area network (can0) important documentation note: the bosch can controller is inte grated in the c8051f04x fam- ily of devices. this section of the data sheet gives a description of the can controller as an overview and offers a description of how the silic on labs cip-51 mcu in terfaces with the on-chi p bosch can controller. in order to use the can controller, please refer to bosch?s c_can user?s manual (revision 1.2) as an accompanying manual to silicon labs? c8051f04x data sheet. the c8051f04x family of devices feature a control area network (can) controller that enables serial com- munication using the can protocol . silicon labs can facilitates co mmunication on a can network in accordance with the bosch specification 2.0a (basic can) and 2.0b (full can). the can controller con- sists of a can core, message ram (separate from the cip-51 ram), a message handler state machine, and control registers. silic on labs can is a protocol controller and does not prov ide physical layer drivers (i.e., transceivers). figure 18.1 shows an example typical configuration on a can bus. silicon labs can operates at bit rates of up to 1 mb it/second, though this can be limited by the physical layer chosen to transmit data on the can bus. the can processor has 32 message objects that can be configured to transmit or receive data. incoming data, message objects and their identifier masks are stored in the can message ram. all pr otocol functions for tran smission of data and acceptance filtering is performed by the can controller and not by the cip-51 mcu. in this way, minimal cpu bandwidth is needed to use can communication. the cip-51 config ures the can controller, accesses received data, and passes data for transmission via special function registers (sfrs) in the cip-51. figure 18.1. typical ca n bus configuration c8051f04x cantx canrx can_h can_l isolation/buffer (optional) can transceiver isolation/buffer (optional) can transceiver isolation/buffer (optional) can transceiver r r can protocol device can protocol device c8051f040/1/2/3/4/5/6/7 228 rev. 1.5 18.1. bosch can cont roller operation the can controller featured in the c8051f04x family of devices is a full implementation of bosch?s full can module and fully complies with can specification 2.0b. a block di agram of the can controller is shown in figure 18.2. the can core provides shifting (cantx and canrx), serial/parallel conversion of messages, and other protocol relat ed tasks such as transmission of dat a and acceptance filtering. the message ram stores 32 message objects which can be received or transmitted on a can network. the can registers and message handler provide an interfac e for data transfer and notification between the can controller and the cip-51. the function and use of the can controller is detailed in the bosch can user?s guide . the user?s guide should be used as a refere nce to configure and use the can contro ller. this silicon labs data sheet describes how to acce ss the can controller. the can controller is typically in itialized using the following steps: step 1. set the sfrpage register to can0_page. step 2. set the init the cce bits to ?1? in the can0cn register. see the can user?s guide for bit definitions. step 3. set timing parameters in the bit timing register and the brp extension register. step 4. initialize each message object or set it?s msgval bit to not valid. step 5. reset the init bit to ?0?. the can control register (can0cn), can test r egister (can0tst), and can status register (can0sta) in the can controller can be accessed direct ly or indirectly via cip-51 sfr?s. all other can registers must be accessed via an indirect indexing method described in section ?18.2.5. using can0adr, can0dath, and candatl to ac cess can registers? on page 232 . figure 18.2. can controller diagram message handler registers message ram (32 message objects) can core tx rx can controller cip-51 mcu interrupt s f r 's cantx canrx c8051f04x s y s c l k can_clk (f sys ) brp prescaler c8051f040/1/2/3/4/5/6/7 rev. 1.5 229 18.1.1. can controller timing the can controller?s system clock (f sys ) is derived from the cip-51 syste m clock (sysclk). note that an external oscillator (such as a quartz crystal) is typica lly required due to the high accuracy requirements for can communication. refer to sectio n ?4.10.4 oscillator tolerance range? in the bosch can user?s guide for further information regarding this topic. 18.1.2. example timing calculation for 1 mbit/sec communication this example shows how to configure the can contoller timing parameters for a 1 mbit/sec bit rate. table 18.1 shows timing-related system parameters needed for the calculation. each bit transmitted on a can network has 4 se gments (sync_seg, prop_seg, phase_seg1, and phase_seg2), as shown in figure 18.3. the sum of these segments determines the can bit time (1/bit rate). in this example, th e desired bit rate is 1 mbit/sec; theref ore, the desired bit time is 1000 ns. figure 18.3. four segmen ts of a can bit time table 18.1. background system information parameter value description cip-51 system clock (sysclk) 22.1184 mhz external oscillator in ?cr ystal oscillator mode?. a 22.1184 mhz quartz crystal is connected between xtal1 and xtal2. can controller system clock (f sys ) 22.1184 mhz derived from sysclk. can clock period (t sys ) 45.211 ns derived from 1/f sys . can time quantum (t q ) 45.211 ns derived from t sys x brp 1,2 can bus length 10 m 5 ns/m signal delay between can nodes. propagation delay time 3 400 ns 2 x (transceiver loop delay + bus line delay) notes: 1. t he can time quantum (t q ) is the smallest unit of time recognized by the can contoller. bit timing parameters are often specified in integer multiples of the time quantum. 2. t he baud rate prescaler (brp) is defined as the val ue of the brp extension r egister plus 1. the brp extension register has a reset value of 0x0000; the baud rate prescaler has a reset value of 1. 3. base d on an iso-11898 compliant transceiver. can does not specify a physical layer. prop_seg phase_seg1 phase_seg2 can bit time (4 to 25 t q ) sync_seg 1t q 1 to 8 t q 1 to 8 t q 1 to 8 t q 1t q sample point c8051f040/1/2/3/4/5/6/7 230 rev. 1.5 we will adjust the length of the 4 bit segments so that their sum is as close as possible to the desired bit time. since each segment must be an inte ger multiple of the time quantum (t q ), the closest achievable bit time is 22 t q (994.642 ns), yielding a bit rate of 1.00539 mbit/sec. the sync_seg is a constant 1 t q . the prop_seg must be greater than or equal to the propagation delay of 400 ns; we choose 9 t q (406.899 ns). the remaining time quanta (t q ) in the bit time are divided between phase_seg1 and phase_seg2 as shown in figure 18.1. we select phase_seg1 = 6 t q and phase_seg2 = 6 t q . equation 18.1. assigning the phase segments the synchronization jump width (sjw) timing parameter is defined by figure 18.2. it is used for determin- ing the value written to the bit timi ng register and for determining the required oscillator tolerance. since we are using a quartz crystal as the system clock sour ce, an oscillator tolerance calculation is not needed. equation 18.2. synchronization jump width (sjw) the value written to the bit timing register can be calculated using equation 18.3. the brp extension register is left at its reset value of 0x0000. equation 18.3. calculating the bit timing register value the following steps are performed to initialize the can timing registers: step 1. set the sfrpage register to can0_page. step 2. set the init the cce bits to ?1? in the can control register accessible through the can0cn sfr. step 3. set the can0adr to 0x03 to point to the bit timing register. phase_seg1 phase_seg2 + bit time sync_seg prop_seg + ?? ? = note 1: if phase_seg1 + phase_seg2 is even, then phase_seg2 = phase_seg1. note 2: phase_seg2 should be at least 2 t q . sjw = min ( 4, phase_seg1 ) brpe = brp - 1 = brp extension register = 0x0000 sjwp = sjw - 1 = min ( 4, 6 ) ? 1 = 3 tseg1 = (prop_seg + phase_seg1 - 1) = 9 + 6 - 1 = 14 tseg2 = (phase_seg2 - 1) = 5 bit timing register = (tseg2 * 0x1000) + (tseg1 * 0x0100) + (sjwp * 0x0040) + brpe = 0x5ec0 c8051f040/1/2/3/4/5/6/7 rev. 1.5 231 step 4. write the value 0x5ec0 to the [can 0dath:can0datl] cip-51 sfrs to set the bit timing register using the indirect indexing method described on section 18.2.5 on page 232 . step 5. perform othe r can initializations. 18.2. can registers can registers are classified as follows: 1. can controller protocol registers : can control, interrupt, error control, bus status, test modes. 2. message object interface registers : used to configure 32 message objects, send and receive data to and from message objects. the cip-51 mcu accesses the can mes- sage ram via the message object interface r egisters. upon writing a message object number to an if1 or if2 command request register, the contents of the associated interface registers (if1 or if2) will be transferred to or from the message object in can ram. 3. message handler registers : these read only registers are used to provide information to the cip-51 mcu about the message object s (msgvld flags, transmission request pending, new data flags) and interrupts p ending (which message objects have caused an interrupt or status interrupt condition). 4. cip-51 mcu special function registers (sfr) : six registers located in the cip-51 mcu memory map that allow direct access to ce rtain can controller protocol registers, and indexed indirect access to all can registers. 18.2.1. can controller protocol registers the can control protocol registers are used to config ure the can controller, process interrupts, monitor bus status, and place the controller in test modes. the can controller protocol registers are accessible using cip-51 mcu sfr?s by an indexed method, and some can be accessed directly by addressing the sfr?s in the cip-51 sfr map for convenience. the registers are: can control register (can0cn), can status register (can0sta), can test register (can0tst), error counter register, bit timing regi ster, and the baud rate prescaler (brp) extension register. can0sta, can0cn, and can0tst can be accessed via cip-51 mcu sfr?s. all others are accessed indirectly using the ca n address indexed method via can0 adr, can0dath, and can0datl. please refer to the bosch can user?s guide for info rmation on the function and use of the can control protocol registers. 18.2.2. message object interface registers there are two sets of message object interface regist ers used to configure the 32 message objects that transmit and receive data to and from the can bus. message objects can be configured for transmit or receive, and are assigned arbitration message iden tifiers for acceptance f iltering by all can nodes. message objects are stored in message ram, and are accessed and configured using the message object interface registers. these registers are accessed via the cip-51?s can0adr and can0dat reg- isters using the indirect indexed address method. please refer to the bosch can user?s guide for information on the function and use of the message object interface registers. c8051f040/1/2/3/4/5/6/7 232 rev. 1.5 18.2.3. message handler registers the message handler registers are read only registers. their flags can be read via the indexed access method with can0adr, can0dath, and can0datl. the message handler registers provide interrupt, error, transmit/receive requests, and new data information. please refer to the bosch can user ?s guide for information on the function and use of the message han- dler registers. 18.2.4. cip-51 mcu special function registers c8051f04x family peripherals are modified, monitore d, and controlled using special function registers (sfr?s). only three of the can controller?s registers may be accessed directly with sfr?s. however, all can controller registers can be accessed indirectly using three cip-51 mcu sfr?s: the can data regis- ters (can0dath and can0datl) and can address register (can0adr). 18.2.5. using can0adr, can0dath, and candatl to access can registers each can controller register has an index number (see table 18.2). the can register address space is 128 words (256 bytes). a can register is acce ssed via the can data registers (can0dath and can0datl) when a can register?s index number is placed into the can address register (can0adr). for example, if the bit timing regi ster is to be configured with a new value, can0adr is loaded with 0x03. the low byte of the desired value is accessed us ing can0datl and the high byte of the bit timing register is accessed using can0dath. can0datl is bit addressable for convenience. to load the value 0x2304 into the bit timing register: can0adr = 0x03; // load bit timing register?s index (table 18.1) can0dath = 0x23; // move the upper byte into data reg high byte can0datl = 0x04; // move the lower byte into data reg low byte note: can0cn, can0sta, and can0tst may be accessed ei ther by using the index method, or by direct access with the cip-51 mcu sfr?s. can0cn is located at sfr location 0xf8/sfr page 1 (sfr definition 18.3), can0tst at 0xdb/sfr page 1 (sfr definition 18.4), and can0sta at 0xc0/sfr page 1 (sfr definition 18.5). 18.2.6. can0adr autoincrement feature for ease of programming message objects, can0adr fe atures autoincrementing for the index ranges 0x08 to 0x12 (interface registers 1) and 0x20 to 0x 2a (interface registers 2). when the can0adr regis- ter has an index in these ranges, the can0adr will autoincrement by 1 to point to the next can reg- ister 16-bit word upon a read/write of can0datl . this speeds programming of the frequently- accessed interface registers when configuring message objects. note: table 18.2 below supersedes figure 5 in sect ion 3, ?programmer?s model? of the bosch can user?s guide. c8051f040/1/2/3/4/5/6/7 rev. 1.5 233 table 18.2. can register index and reset values can register index register name reset va lue notes 0x00 can control register 0x0001 accessible in cip-51 sfr map 0x01 status register 0x0000 accessible in cip-51 sfr map 0x02 error register 0x0000 read only 0x03 bit timing register 0x2301 write enabled by cce bit in can0cn 0x04 interrupt register 0x0000 read only 0x05 test register 0x0000 bit 7 (rx) is determined by can bus 0x06 brp extension register 0x0000 write enabled by test bit in can0cn 0x08 if1 command request 0x0001 can0adr autoincrements in if1 index space ( 0x08 - 0x12) upon write to can0datl 0x09 if1 command mask 0x0000 can0adr autoincremen t upon write to can0datl 0x0a if1 mask 1 0xffff can0adr autoincremen t upon write to can0datl 0x0b if1 mask 2 0xffff can0adr autoincremen t upon write to can0datl 0x0c if1 arbitration 1 0x0000 can0adr autoincremen t upon write to can0datl 0x0d if1 arbitration 2 0x0000 can0adr autoincremen t upon write to can0datl 0x0e if1 message control 0x0000 can0adr autoincremen t upon write to can0datl 0x0f if1 data a1 0x0000 can0adr autoincremen t upon write to can0datl 0x10 if1 data a2 0x0000 can0adr autoincremen t upon write to can0datl 0x11 if1 data b1 0x0000 can0adr autoincremen t upon write to can0datl 0x12 if1 data b2 0x0000 can0adr autoincremen t upon write to can0datl 0x20 if2 command request 0x0001 can0adr autoincrements in if2 index space (0x20 - 0x2a) upon write to can0datl 0x21 if2 command mask 0x0000 can0adr autoincremen t upon write to can0datl 0x22 if2 mask 1 0xffff can0adr autoincremen t upon write to can0datl 0x23 if2 mask 2 0xffff can0adr autoincremen t upon write to can0datl 0x24 if2 arbitration 1 0x0000 can0adr autoincremen t upon write to can0datl 0x25 if2 arbitration 2 0x0000 can0adr autoincremen t upon write to can0datl c8051f040/1/2/3/4/5/6/7 234 rev. 1.5 0x26 if2 message control 0x0000 can0adr autoincremen t upon write to can0datl 0x27 if2 data a1 0x0000 can0adr autoincremen t upon write to can0datl 0x28 if2 data a2 0x0000 can0adr autoincremen t upon write to can0datl 0x29 if2 data b1 0x0000 can0adr autoincremen t upon write to can0datl 0x2a if2 data b2 0x0000 can0adr autoincremen t upon write to can0datl 0x40 transmission request 1 0x0000 transmission request flags for message objects ( read only) 0x41 transmission request 2 0x0000 transmission request flags for message objects ( read only) 0x48 new data 1 0x0000 new data flags for message objects (read only) 0x49 new data 2 0x0000 new data flags for message objects (read only) 0x50 interrupt pending 1 0x0000 interrupt pending flags for message objects ( read only) 0x51 interrupt pending 2 0x0000 interrupt pending flags for message objects ( read only) 0x58 message valid 1 0x0000 message valid flags for message objects (read on ly) 0x59 message valid 2 0x0000 message valid flags for message objects (read on ly) table 18.2. can regi ster index and reset values (continued) can register index register name reset value notes figure 18.4. can0dath : can data access re gister high byte bit7-0: can0dath: can data access register high byte. the can0dat registers are used to read/write register values and data to and from the can registers pointed to with the index number in the can0adr register. the can0adr register is used to point th e [can0dath:can0datl] to a desired can register. the desired can register?s inde x number is moved into can0adr. the can0dat register can then read/write to and from the can register. r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: sfr page: 0xd9 1 c8051f040/1/2/3/4/5/6/7 rev. 1.5 235 sfr definition 18.1. can0datl: can data a ccess register low byte sfr definition 18.2. can0adr: can address index bit7-0: can0datl: can data access register low byte. the can0dat registers are used to read/write register values and data to and from the can registers pointed to with the index number in the can0adr register. the can0adr register is used to point th e [can0dath:can0datl] to a desired can register. the desired can register?s inde x number is moved into can0adr. the can0dat register can then read/write to and from the can register. r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000001 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: sfr page: 0xd8 1 bit7-0: can0adr: can address index register. the can0adr register is used to point th e [can0dath:can0datl] to a desired can register. the desired can register?s inde x number is moved into can0adr. the can0dat register can then read/write to and from the can register. note : when the value of can0adr is 0x08-0x12 and 0x20-0x2a (if1 and if2 registers), this register will autoincrement by 1 upon a write to can0datl. see section ?18.2.6. can0adr autoincrement feature? on page 232 . all can registers? functions/definitions ar e listed and described in the bosch can user?s guide. r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: sfr page: 0xda 1 c8051f040/1/2/3/4/5/6/7 236 rev. 1.5 sfr definition 18.3. can0cn: can control sfr definition 18.4. can0tst: can test bit 4: canif: can interrupt flag. write = don?t care. 0: can interrupt has not occurred. 1: can interrupt has occurred and is active. canif is controlled by the can controller and is cleared by hardware once all interrupt con- ditions have been cleared in the can controller. see section 3.4.1 in the bosch can user?s guide (page 24) for more information concerning can controller interrupts. *all can registers? functions/definitions are listed and described in the bosch can user?s guide with the exception of the canif bit. this register may be accessed directly in the cip-51 sfr register space, or through the indi- rect, index method (see section ? 18.2.5. using can0adr, can0dath, and candatl to access can registers ? on page 232 ). r/w r/w r/w r r/w r/w r/w r/w reset value ***canif*** * bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: sfr page: 0xf8 1 all can registers? functions/definitions ar e listed and described in the bosch can user?s guide. this register may be accessed directly in the cip-51 sfr register space, or through the indi- rect, index method (see section ? 18.2.5. using can0adr, can0dath, and candatl to access can registers ? on page 232 ). r/w r/w r/w r/w r/w r/w r/w r/w reset value please see the bosch can user?s guide for a complete definition of this register bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: sfr page: 0xdb 1 c8051f040/1/2/3/4/5/6/7 rev. 1.5 237 sfr definition 18.5. can0sta: can status all can registers? functions/definitions ar e listed and described in the bosch can user?s guide. this register may be accessed directly in the cip-51 sfr register space, or through the indi- rect, index method (see section ? 18.2.5. using can0adr, can0dath, and candatl to access can registers ? on page 232 ). r/w r/w r/w r/w r/w r/w r/w r/w reset value please see the bosch can user?s guide for a complete definition of this register bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: sfr page: 0xc0 1 c8051f040/1/2/3/4/5/6/7 238 rev. 1.5 c8051f040/1/2/3/4/5/6/7 rev. 1.5 239 19. system management bus/i 2 c bus (smbus0) the smbus0 i/o interface is a two-wire, bi-directional serial bus. smbus0 is compliant with the system management bus specification, vers ion 2, and compatible with the i 2 c serial bus. reads and writes to the interface by the system controller ar e byte oriented with the smbus0 interface autonomously controlling the serial transfer of the data. a me thod of extending the clock-low duration is available to accommodate devices with different speed capabilities on the same bus. smbus0 may operate as a master and/or slave, and ma y function on a bus with multiple masters. smbus0 provides control of sda (serial data), scl (serial cloc k) generation and synchroniz ation, arbitration logic, and start/stop control and generation. smbus0 is controlled by sfrs as described in section 19.4 on page 245 . figure 19.1. smbus0 block diagram sfr bus data path control sfr bus write to smb0dat smbus control logic read smb0dat smb0adr s l v 6 g c s l v 5 s l v 4 s l v 3 s l v 2 s l v 1 s l v 0 c r o s s b a r clock divide logic sysclk smb0cr c r 7 c r 6 c r 5 c r 4 c r 3 c r 2 c r 1 c r 0 scl filter n sda control 0000000b 7 msbs 8 ab a=b 8 0 1 2 3 4 5 6 7 smb0dat 8 smb0cn s t a s i a a f t e t o e e n s m b b u s y s t o smb0sta s t a 4 s t a 3 s t a 2 s t a 1 s t a 0 scl control status generation arbitration scl synchronization scl generation (master mode) irq generation s t a 5 s t a 6 s t a 7 ab a=b smbus irq interrupt request port i/o 1 0 sda filter n 7 c8051f040/1/2/3/4/5/6/7 240 rev. 1.5 figure 19.2 shows a typical smbus configuration. the smbu s0 interface will work at any voltage between 3.0 v and 5.0 v and different devices on the bus may op erate at different voltage levels. the bi-directional scl (serial clock) and sda (serial data) lines must be connected to a positive power supply voltage through a pullup resistor or similar circuit. every devi ce connected to the bus must have an open-drain or open-collector output for both the scl and sda lines, so that both are pulled high when the bus is free. the maximum number of devices on the bus is limited only by the requirement that the rise and fall times on the bus will not exceed 300 ns and 1000 ns, respectively. figure 19.2. typical smbus configuration 19.1. supporting documents it is assumed the reader is fam iliar with or has access to th e following supporting documents: ?i 2 c manual (an10216-01) -- march 24 , 2003, philips semiconductor. ? system management bus specification -- version 1.1, sbs implementers forum. v dd = 5 v master device slave device 1 slave device 2 v dd = 3 v v dd = 5 v v dd = 3 v sda scl c8051f040/1/2/3/4/5/6/7 rev. 1.5 241 19.2. smbus protocol two types of data transfers are possible: data transfers from a master transmitter to an addressed slave receiver (write), and data transfers from an addres sed slave transmitter to a master receiver (read). the master device initiates both types of data transfer s and provides the serial clock pulses on scl. note: multiple master devices on the same bus are supported. if two or more masters attempt to initiate a data transfer simultaneously, an arbitration scheme is empl oyed with a single master always winning the arbitra- tion. note that it is not necessary to specify one device as the master in a system; any device who trans- mits a start and a slave address becomes the master for that transfer. a typical smbus transaction consists of a start cond ition followed by an address byte (bits7-1: 7-bit slave address; bit0: r/w direction bit), one or more byte s of data, and a stop condition. each byte that is received (by a master or slave) must be acknow ledged (ack) with a low sda during a high scl (see figure 19.3). if the receiving devic e does not ack, the tr ansmitting device will read a ?not acknowledge? (nack), which is a high sda during a high scl. the direction bit (r/w) occupies the le ast-significant bit position of the ad dress. the direction bit is set to logic 1 to indicate a "read" operation and clear ed to logic 0 to indicate a "write" operation. all transactions are initiated by a master, with one or more addressed slave devices as the target. the master generates the start condition and then transmit s the slave address and dire ction bit. if the trans- action is a write operation from the master to the slav e, the master transmits the data one byte at a time and expects an ack from the slave at the end of each byte. for read operations, the slave transmits the data and expects an ack from the master at the end of each byte. at the end of the data transfer, the mas- ter generates a stop condition to te rminate the transacti on and free the bus. figure 19.3 illustrates a typ- ical smbus transaction. figure 19.3. smbus transaction 19.2.1. arbitration a master may start a transfer only if the bus is free. th e bus is free after a stop condition or after the scl and sda lines remain high for a specified time (see section 19.2.4 ). in the event that two or more devices attempt to begin a transfer at the same time, an arbi tration scheme is employed to force one master to give up the bus. the master devices continue transmitting until one attempts a high while the other transmits a low. since the bus is open- drain, the bus will be pulled low. the master attempting the high will detect a low sda and give up the bus. the winning master continues its transmission without interruption; the losing master becomes a slave and receives the rest of the transfer. this arbitration scheme is non- destructive: one device always wins, and no data is lost. sla6 sda sla5-0 r/w d7 d6-0 scl slave address + r/w data byte start ack nack stop c8051f040/1/2/3/4/5/6/7 242 rev. 1.5 19.2.2. clock low extension smbus provides a clock synchron ization mechanism, similar to i 2 c, which allows devices with different speed capabilities to coexist on the bus. a clock-low extension is used du ring a transfer in order to allow slower slave devices to communica te with faster masters. the slave may temporarily hold the scl line low to extend the clock low period, effectively decreasing the serial clock frequency. 19.2.3. scl low timeout if the scl line is held low by a slave device on the bus, no further communication is possible. furthermore, the master cannot force the scl line high to correct th e error condition. to solve this problem, the smbus protocol specifies that devices participating in a tran sfer must detect any clock cy cle held low longer than 25 ms as a ?timeout? condition. devices that have detected the timeout conditi on must reset the communi- cation no later than 10 ms after detecting the timeout condition. 19.2.4. scl high (smbus free) timeout the smbus specification stipulates th at if the scl and sda lines remain high for more that 50 s, the bus is designated as free. if an smbus device is waiting to generat e a master start, the start will be gen- erated following the bus free timeout. 19.3. smbus transfer modes the smbus0 interface may be configured to operate as a master and/or a slave. at any particular time, the interface will be operating in one of the following modes: master transmitter, master receiver, slave transmitter, or slave receiver. see table 19.1 for transfer mode status decoding using the smb0sta sta- tus register. the following mode descriptions illustrate an interrupt-dr iven smbus0 application; smbus0 may alternatively be operated in polled mode. 19.3.1. master transmitter mode serial data is transmitted on sda while the serial clock is output on scl. smbus0 generates a start condition and then transmits the first byte containing the address of the target slave device and the data direction bit. in this case the data direction bit (r/w) will be logic 0 to indicate a "write" operation. the smbus0 interface transmits one or more bytes of serial data, waiting for an acknowledge (ack) from the slave after each byte. to indicate the end of the serial transfer, smbus0 generates a stop condition. figure 19.4. typical mast er transmitter sequence a a a s w p data byte data byte sla s = start p = stop a = ack w = write sla = slave address received by smbus interface transmitted by smbus interface interrupt interrupt interrupt interrupt c8051f040/1/2/3/4/5/6/7 rev. 1.5 243 19.3.2. master receiver mode serial data is received on sda while the serial cloc k is output on scl. the smbus0 interface generates a start followed by the first data byte containing the addr ess of the target slave and the data direction bit. in this case the data direction bit (r/w) will be logi c 1 to indicate a "read" ope ration. the smbus0 inter- face receives serial data from the slave and generates the clock on scl. after each byte is received, smbus0 generates an ack or nack depending on t he state of the aa bit in register smb0cn. smbus0 generates a stop condition to indicate the end of the serial transfer. figure 19.5. typical m aster receiver sequence 19.3.3. slave transmitter mode serial data is transmitted on sda while the serial clo ck is received on scl. the smbus0 interface receives a start followed by data byte containing the slave address and direction bit. if the received slave address matches the address held in regi ster smb0adr, the smbu s0 interface generate s an ack. smbus0 will also ack if the general call address (0x00) is received and the general call address enable bit (smb0adr.0) is set to logic 1. in th is case the data direction bit (r/w) will be logic 1 to indicate a "read" operation. the smbus0 interface receives the clock on scl and transmits one or more bytes of serial data, waiting for an ack from the master after each byte. smbus0 exits slave mode after receiving a stop condition from the master. figure 19.6. typical sl ave transmitter sequence data byte data byte a n a s r p sla s = start p = stop a = ack n = nack r = read sla = slave address received by smbus interface transmitted by smbus interface interrupt interrupt interrupt interrupt p r sla s data byte data byte a n a s = start p = stop n = nack w = write sla = slave address received by smbus interface transmitted by smbus interface interrupt interrupt interrupt interrupt c8051f040/1/2/3/4/5/6/7 244 rev. 1.5 19.3.4. slave receiver mode serial data is received on sda while the serial clock is received on scl. the smbus0 interface receives a start followed by data byte containing the slave addr ess and direction bit. if the received slave address matches the address held in regist er smb0adr, the interface generates an ack. smbus0 will also ack if the general call address (0x00) is received and the g eneral call address enable bi t (smb0adr.0) is set to logic 1. in this case the data direction bit (r/w) will be logic 0 to indicate a "write" operation. the smbus0 interface receives one or more bytes of seri al data; after each byte is received, the interface transmits an ack or nack depending on the state of the aa bit in smb0cn. smbus0 exits slave receiver mode after receiving a stop condition from the master. figure 19.7. typical sl ave receiver sequence p w sla s data byte data byte a a a s = start p = stop a = ack r = read sla = slave address received by smbus interface transmitted by smbus interface interrupt interrupt interrupt interrupt c8051f040/1/2/3/4/5/6/7 rev. 1.5 245 19.4. smbus special function registers the smbus0 serial interface is accessed and cont rolled through five sfrs: smb0cn control register, smb0cr clock rate register, smb0adr address regi ster, smb0dat data register and smb0sta sta- tus register. the five special function registers related to the operation of the smbus0 interface are described in the following sections. 19.4.1. control register the smbus0 control register smb0cn is used to conf igure and control the smbus0 interface. all of the bits in the register can be read or written by software. two of the control bits are also affected by the smbus0 hardware. the serial interrupt flag (si, smb0cn.3) is set to logic 1 by the hardware when a valid serial interrupt condition occurs. it can only be cleared by software. the stop flag (sto, smb0cn.4) is set to logic 1 by software. it is cleared to logic 0 by hardware when a stop condition is detected on the bus. setting the ensmb flag to logic 1 enables the smbus0 interface. clearing the ensmb flag to logic 0 dis- ables the smbus0 interface and removes it from the bus. momentarily clearing the ensmb flag and then resetting it to logic 1 will reset smbu s0 communication. however, ensm b should not be used to tempo- rarily remove a device from the bus since the bus state information will be lo st. instead, the assert acknowledge (aa) flag should be used to temporarily remove the device from the bus (see description of aa flag below). setting the start flag (sta, smb0cn.5) to logic 1 will put smbus0 in a master mode. if the bus is free, smbus0 will generate a start condition. if the bus is not free, smbus0 wa its for a stop condition to free the bus and then generates a start condition after a 5 s delay per the smb0cr value (in accordance with the smbus protocol, the smbus0 interface also considers the bus free if the bus is idle for 50 s and no stop condition was recognized). if sta is set to logic 1 while smbus0 is in master mode and one or more bytes have bee n transferred, a re peated start conditio n will be generated. when the stop flag (sto, smb0cn.4) is set to logic 1 while the smbus0 interfac e is in master mode, the interface generates a stop condition. in a slave mode, the sto flag may be used to recover from an error condition. in this case, a stop co ndition is not generated on the bus, but the smbus hardware behaves as if a stop condition has been received and enters the "not addressed" slave receiver mode. note that this simulated stop will not cause the bus to appear free to smbus0. the bus will remain occupied until a stop appears on the bus or a bus free timeout occurs. hardware automatically clears the sto flag to logic 0 when a stop condition is detected on the bus. the serial interrupt flag (si, smb0cn.3) is set to logic 1 by hard ware when the smbus0 interface enters any one of the 28 possible states except the idle state. if interrupts are enabled for the smbus0 interface, an interrupt request is generated when the si flag is set. the si flag must be cleared by software. important note: if si is set to logic 1 while the scl line is low, the clock-low period of the serial clock will be stretched and the serial transfer is suspended until si is cleared to logic 0. a high level on scl is not affected by the setting of the si flag. the assert acknowledge flag (aa, smb0cn.2) is used to set the level of the sda line during the acknowl- edge clock cycle on the scl line. sett ing the aa flag to logic 1 will cause an ack (low level on sda) to be sent during the acknowledge cycle if the device has been addressed. setting the aa flag to logic 0 will cause a nack (high level on sda) to be sent during acknowledge cycle. after the transmission of a byte in slave mode, the slave can be temporarily removed from the bus by clearing the aa flag. the slave's own address and general ca ll address will be ignored. to resume operation on the bus, the aa flag must be reset to logic 1 to allow the slave's address to be recognized. c8051f040/1/2/3/4/5/6/7 246 rev. 1.5 setting the smbus0 free timer enable bit (fte, smb0cn.1) to logic 1 enables the timer in smb0cr. when scl goes high, the timer in smb0cr counts up. a timer overflow indicate s a free bus timeout: if smbus0 is waiting to generate a start, it will do so after this timeout. the bus free period should be less than 50 s (see sfr definition 19 .2, smbus0 clock rate register). when the toe bit in smb0cn is set to logic 1, timer 4 is used to detect scl low timeouts. if timer 4 is enabled (see section ?23.2. timer 2, time r 3, and timer 4? on page 295 ), timer 4 is forced to reload when scl is high, and forced to count when scl is lo w. with timer 4 enabled and configured to overflow after 25 ms (and toe set), a timer 4 overflow indicate s a scl low timeout; the timer 4 interrupt service routine can then be used to reset smbus0 commu nication in the event of an scl low timeout. c8051f040/1/2/3/4/5/6/7 rev. 1.5 247 sfr definition 19.1. smb0cn: smbus0 control bit7: busy: busy status flag. 0: smbus0 is free 1: smbus0 is busy bit6: ensmb: smbus enable. this bit enables/disables the smbus serial interface. 0: smbus0 disabled. 1: smbus0 enabled. bit5: sta: smbus start flag. 0: no start condition is transmitted. 1: when operating as a master, a start conditi on is transmitted if the bus is free. (if the bus is not free, the start is transmitted after a stop is received.) if sta is set after one or more bytes have been transmitted or received and before a stop is received, a repeated start condition is transmitted. bit4: sto: smbus stop flag. 0: no stop condition is transmitted. 1: setting sto to logic 1 causes a stop conditi on to be transmitted. when a stop condi- tion is received, hardware clears sto to logi c 0. if both sta and sto are set, a stop con- dition is transmitted followed by a start co ndition. in slave mode, setting the sto flag causes smbus to behave as if a stop condition was received. bit3: si: smbus seri al interrupt flag. this bit is set by hardware when one of 27 po ssible smbus0 states is entered. (status code 0xf8 does not cause si to be set.) when the si interrupt is enabled, se tting this bit causes the cpu to vector to the smbu s interrupt service routine. th is bit is not automatically cleared by hardware and must be cleared by software. bit2: aa: smbus assert acknowledge flag. this bit defines the type of acknowledge retu rned during the acknowledge cycle on the scl line. 0: a "not acknowledge" (high level on sda) is returned during the acknowledge cycle. 1: an "acknowledge" (low level on sda) is returned during the acknowledge cycle. bit1: fte: smbus free timer enable bit 0: no timeout when scl is high 1: timeout when scl high time exceeds limit specified by the smb0cr value. bit0: toe: smbus timeout enable bit 0: no timeout when scl is low. 1: timeout when scl low time exceeds lim it specified by timer 4, if enabled. r r/w r/w r/w r/w r/w r/w r/w reset value busy ensmb sta sto si aa fte toe 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 bit addressable sfr address: sfr page: 0xc0 0 c8051f040/1/2/3/4/5/6/7 248 rev. 1.5 19.4.2. clock rate register sfr definition 19.2. smb0cr: smbus0 clock rate bits7-0: smb0cr.[7:0]: smbus0 clock rate preset the smb0cr clock rate register controls the frequency of the serial clock scl in master mode. the 8-bit word stored in the smb0cr r egister preloads a dedicated 8-bit timer. the timer counts up, and when it rolls over to 0x00, the scl logic state toggles. the smb0cr setting should be bounded by the following equation, where smb0cr is the unsigned 8-bit value in register smb0cr, and sysclk is the system clock frequency in hz: the resulting scl signal high and low times are given by the following equations: using the same value of smb0cr from above, the bus free timeout period is given in the following equation: r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: sfr page: 0xcf 0 smb0 cr 288 0.85 ? sysclk ? ?? ? ?? ? t low 256 smb 0 cr ? ?? sysclk ? t high 258 smb0 cr ? ?? sysclk ? ns + ? t bft 10 256 smb0 cr ? ?? sysclk ------------------- --------------------------------- - ?? c8051f040/1/2/3/4/5/6/7 rev. 1.5 249 19.4.3. data register the smbus0 data register smb0dat holds a byte of serial data to be transmitted or one that has just been received. software can read or write to this regist er while the si flag is set to logic 1; software should not attempt to access the smb0dat register when t he smbus is enabled and the si flag reads logic 0 since the hardware may be in the process of shifting a byte of data in or out of the register. data in smb0dat is always shifted ou t msb first. after a byte has been received, the first bit of received data is located at the msb of smb0dat. while data is being shifted out, data on the bus is simultaneously being shifted in. therefore, smb0dat always contains t he last data byte present on the bus. in the event of lost arbitration, the transition from master transmitter to slave receiver is made with the correct data in smb0dat. sfr definition 19.3. smb0dat: smbus0 data 19.4.4. address register the smb0adr address register holds the slave addre ss for the smbus0 interface. in slave mode, the seven most-significant bits hold the 7-bit slave address. the least significant bit (bit0) is used to enable the recognition of the gene ral call address (0x00). if bit0 is set to logic 1, the general call address will be recog- nized. otherwise, the general call address is ignored . the contents of this register are ignored when smbus0 is operating in master mode. bits7-0: smb0dat: smbus0 data. the smb0dat register contains a byte of data to be transmitted on the smbus0 serial inter- face or a byte that has just been received on the smbus0 serial interface. the cpu can read from or write to this register whenever t he si serial interrupt flag (smb0cn.3) is set to logic 1. when the si flag is not set, the syste m may be in the process of shifting data and the cpu should not attempt to access this register. r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: sfr page: 0xc2 0 c8051f040/1/2/3/4/5/6/7 250 rev. 1.5 sfr definition 19.4. smb0adr: smbus0 address 19.4.5. status register the smb0sta status register holds an 8-bit status c ode indicating the current state of the smbus0 inter- face. there are 28 possible smbus0 states, each with a corresponding unique status code. the five most significant bits of the status code vary while the three least-significant bits of a valid status code are fixed at zero when si = ?1?. therefore, all po ssible status codes are multiples of eight. this facilitates the use of sta- tus codes in software as an index used to branch to appropriate service routines (allowing 8 bytes of code to service the state or jump to a more extensive service routine). for the purposes of user software, the contents of the sm b0sta register is only defi ned when the si flag is logic 1. software should never write to the smb0sta register; doing so will yield indeterm inate results. the 28 smbus0 states, along with their correspondi ng status codes, are given in table 19.1. bits7-1: slv6-slv0: smbus0 slave address. these bits are loaded with the 7-bit slave address to which smbus0 will respond when oper- ating as a slave transmitter or slave receiver. slv6 is the most significant bit of the address and corresponds to the first bit of the address byte received. bit0: gc: general call address enable. this bit is used to enable general call address (0x00) recognition. 0: general call address is ignored. 1: general call address is recognized. r/wr/wr/wr/wr/wr/wr/w r/wreset value slv6 slv5 slv4 slv3 slv2 slv1 slv0 gc 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: sfr page: 0xc3 0 c8051f040/1/2/3/4/5/6/7 rev. 1.5 251 sfr definition 19.5. smb0sta: smbus0 status bits7-3: sta7-sta3: smbus0 status code. these bits contain the smbus0 status code. th ere are 28 possible status codes; each sta- tus code corresponds to a single smbus state. a valid status code is present in smb0sta when the si flag (smb0cn.3) is set to logic 1. the content of smb0sta is not defined when the si flag is logic 0. writing to the smb0st a register at any time will yield indeterminate results. bits2-0: sta2-sta0: the three least significant bi ts of smb0sta are always read as logic 0 when the si flag is logic 1. r/w r/w r/w r/w r/w r/w r/w r/w reset value sta7 sta6 sta5 sta4 sta3 sta2 sta1 sta0 11111000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: sfr page: 0xc1 0 c8051f040/1/2/3/4/5/6/7 252 rev. 1.5 table 19.1. smb0sta status codes and states mode status code smbus state typical action mt/ mr 0x08 start condition transmitted. load smb0dat with slave address + r/w. clear sta. 0x10 repeated start condition transmitted. load smb0dat with slave address + r/w. clear sta. master transmitter 0x18 slave address + w transmitted. ack r eceived. load smb0dat with data to be transmit - ted. 0x20 slave address + w transmitted. nack r eceived. acknowledge poll to retry. set sto + st a. 0x28 data byte transmitt ed. ack received. 1) load smb0dat with next byte, or 2) set sto, or 3) clear sto then set sta for repeated st art. 0x30 data byte transmitted. nack received. 1) retry transfer or 2) set sto. 0x38 arbitration lost. save current data. master receiver 0x40 slave address + r transmitted. ack received. if only receiving one byte, clear aa (send nack a fter received byte). wait for received data. 0x48 slave address + r transmitted. nack r eceived. acknowledge poll to retry. set sto + st a. 0x50 data byte received. ack transmitted. read smb0dat. wait for next byte. if next byte is last byte, clear aa. 0x58 data byte received. nack transmitted. set sto. c8051f040/1/2/3/4/5/6/7 rev. 1.5 253 slave receiver 0x60 own slave address + w received. ack trans - mitted. wait for data. 0x68 arbitration lost in sending sla + r/w as mas - ter. own address + w received. ack transmit - ted. save current data for retry when bus is free . wait for data. 0x70 general call address received. ack transmit - ted. wait for data. 0x78 arbitration lost in sending sla + r/w as mas - ter. general call address received. ack trans - mitted. save current data for retry when bus is free . 0x80 data byte received. ack transmitted. read smb0dat. wait for next byte or st op. 0x88 data byte received. nack transmitted. set sto to reset smbus. 0x90 data byte received after general call address. ac k transmitted. read smb0dat. wait for next byte or st op. 0x98 data byte received after general call address. nack transmitted. set sto to reset smbus. 0xa0 stop or repeated start received. no action necessary. slave transmitter 0xa8 own address + r received. ack transmitted. load smb0dat with data to transmit. 0xb0 arbitration lost in transmitting sla + r/w as ma ster. own address + r received. ack transmitted. save current data for retry when bus is free . load smb0dat with data to trans - mit. 0xb8 data byte transmitt ed. ack received. load smb0dat with data to transmit. 0xc0 data byte transmitted. nack received. wait for stop. 0xc8 last data byte transmitted (aa=0). ack r eceived. set sto to reset smbus. slave 0xd0 scl clock high timer per smb0cr timed out set sto to reset smbus. all 0x00 bus error (illegal start or stop) set sto to reset smbus. 0xf8 idle state does not set si. table 19.1. smb0sta status codes and stat es (continued) mode status code smbus state typical action c8051f040/1/2/3/4/5/6/7 254 rev. 1.5 c8051f040/1/2/3/4/5/6/7 rev. 1.5 255 20. enhanced serial peri pheral interface (spi0) the enhanced serial peripheral interface (spi0) prov ides access to a flexible, full-duplex synchronous serial bus. spi0 can operate as a master or slave device in both 3-wire or 4-wire modes, and supports mul- tiple masters and slaves on a single spi bus. the slave-select (nss) signal can be configured as an input to select spi0 in slave mode, or to disable master mode operation in a multi-master environment, avoiding contention on the spi bus when more than one master attempts simultaneous data transfers. nss can also be configured as a chip-select output in master mode, or disabled for 3-wire operation. additional gen- eral purpose port i/o pins can be used to se lect multiple slave dev ices in master mode. figure 20.1. spi block diagram sfr bus data path control sfr bus write spi0dat receive data buffer spi0dat 0 1 2 3 4 5 6 7 shift register spi control logic spi0ckr scr7 scr6 scr5 scr4 scr3 scr2 scr1 scr0 spi0cfg spi0cn pin interface control pin control logic c r o s s b a r port i/o read spi0dat spi irq tx data rx data sck mosi miso nss transmit data buffer clock divide logic sysclk ckpha ckpol slvsel nssmd1 nssmd0 spibsy msten nssin srmt rxbmt spif wcol modf rxovrn txbmt spien c8051f040/1/2/3/4/5/6/7 256 rev. 1.5 20.1. signal descriptions the four signals used by spi0 (mosi, miso, sck, nss) are described below. 20.1.1. master out, slave in (mosi) the master-out, slave-in (mosi) signal is an output fr om a master device and an input to slave devices. it is used to serially transfer data from the master to th e slave. this signal is an output when spi0 is operat- ing as a master and an input when spi0 is operating as a slave. data is transferred most-significant bit first. when configured as a master, mosi is driven by the msb of the shift register in both 3- and 4-wire mode. 20.1.2. master in, slave out (miso) the master-in, slave-out (miso) signal is an output from a slave device and an input to the master device. it is used to serially transfer data from the slave to the master. this signal is an input when spi0 is operat- ing as a master and an output when spi0 is operating as a slave. data is transferred most-significant bit first. the miso pin is placed in a high-impedance stat e when the spi module is disabled and when the spi operates in 4-wire mode as a slave that is not select ed. when acting as a slave in 3-wire mode, miso is always driven by the msb of the shift register. 20.1.3. serial clock (sck) the serial clock (sck) signal is an output from the mast er device and an input to slave devices. it is used to synchronize the transfer of data between the mast er and slave on the mosi and miso lines. spi0 gen- erates this signal when operating as a master. the sck signal is ignored by a spi slave when the slave is not selected (nss = 1) in 4-wire slave mode. 20.1.4. slave select (nss) the function of the slave-select (nss) signal is dependent on the setting of the nssmd1 and nssmd0 bits in the spi0cn register. there are three possib le modes that can be selected with these bits: 1. nssmd[1:0] = 00: 3-wire master or 3-wire slave mode: spi0 operates in 3-wire mode, and nss is disabled. when operating as a slave dev ice, spi0 is always selected in 3-wire mode. since no select signal is present, spi0 can be th e only slave on the bus in 3-wire mode. this is intended for point-to-point communication between a master and one slave. 2. nssmd[1:0] = 01: 4-wire slave or multi-ma ster mode: spi0 operates in 4-wire mode, and nss is enabled as an input. when operating as a slave, nss selects the spi0 device. when operating as a master, a 1-to-0 transition of th e nss signal disables t he master function of spi0 so that multiple master devices can be used on the same spi bus. 3. nssmd[1:0] = 1x: 4-wire master mode: spi0 oper ates in 4-wire mode, and nss is enabled as an output. the setting of nssm d0 determines what logic leve l the nss pin will output. this configuration should only be used wh en operating spi0 as a master device. see figure 20.2, figure 20.3, and figure 20.4 for typi ca l connection diagrams of the various operational modes. note that the setting of nssmd bits affects the pinout of the device. when in 3-wire master or 3-wire slave mode, the nss pin will not be mapped by the crossbar. in all other modes, the nss signal will be mapped to a pin on the device. see section ? 17.1. ports 0 through 3 and the priority crossbar decoder ? on page 204 for general purpose port i/o and crossbar information. c8051f040/1/2/3/4/5/6/7 rev. 1.5 257 20.2. spi0 master mode operation a spi master device initiates all data transfers on a spi bus. spi0 is placed in master mode by setting the master enable flag (msten, spi0cn.6). writing a byte of data to the spi0 data register (spi0dat) when in master mode writes to the transmit buffer. if the spi shift register is empty, the byte in the transmit buffer is moved to the shift register, and a data transfer begins. the spi0 master immediately shifts out the data serially on the mosi line while provid ing the serial clock on sck. the spi f (spi0cn.7) flag is set to logic 1 at the end of the transfer. if interrupts are enabl ed, an interrupt request is generated when the spif flag is set. while the spi0 master transf ers data to a slave on the mosi line, the addressed spi slave device simultaneously transfers the contents of its shift register to the spi master on the miso line in a full-duplex operation. therefore, the spif flag serves as both a transmit-complete and receive-data-ready flag. the data byte received from the slave is transferred msb-fi rst into the master's shift register. when a byte is fully shifted into the register, it is moved to the receive buffer where it can be read by the processor by reading spi0dat. when configured as a master, spi0 can operate in one of three different modes: multi-master mode, 3-wire single-master mode, and 4-wire single-master mode. the default, multi-master mode is active when nssmd1 (spi0cn.3) = 0 and nssmd0 (spi0cn.2) = 1. in this mode, nss is an input to the device, and is used to disable the master spi0 when another mast er is accessing the bus. when nss is pulled low in this mode, msten (spi0cn.6) and spien (spi0cn.0) are set to 0 to disable the spi master device, and a mode fault is generate d (modf, spi0cn.5 = 1). mode fault will gen erate an inte rrupt if e nabled. spi0 must be manually re-enabled in soft ware under these circumstances. in multi-master systems, devices will typically default to being slave devices while they are not acting as the system master device. in multi-mas- ter mode, slave devices can be addressed individua lly (if needed) using general-purpose i/o pins. figure 20.2 shows a connection diagram between two master devices in multiple-mas ter mode. 3-wire single-master mode is active when nssmd1 (s pi0cn.3) = 0 and nssmd0 ( spi0cn.2) = 0. in this mode, nss is not used, and does not get mapped to an external port pin through the crossbar. any slave devices that must be addressed in this mode should be selected using general-purpose i/o pins. figure 20.3 shows a connection diagram between a ma ster device in 3-wire master mode and a slave device. 4-wire single-master mode is active when nssmd1 (spi0cn.3) = 1. in this mode, nss is configured as an output pin, and can be used as a slave-select signal for a single spi dev ice. in this mode, the output value of nss is controlled (in software) with the bit nssm d0 (spi0cn.2). additional slave devices can be addressed using general-purpose i/o pins. figure 20.4 shows a connection diagram for a master device in 4-wire master mode and two slave devices. c8051f040/1/2/3/4/5/6/7 258 rev. 1.5 figure 20.2. multiple-master mode connect ion diagram figure 20.3. 3-wire single master and slave mode connection diagram figure 20.4. 4-wire single master and slave mode co nnection diagram master device 2 master device 1 mosi miso sck miso mosi sck nss gpio nss gpio slave device master device mosi miso sck miso mosi sck slave device master device mosi miso sck miso mosi sck nss nss gpio slave device mosi miso sck nss c8051f040/1/2/3/4/5/6/7 rev. 1.5 259 20.3. spi0 slave mode operation when spi0 is enabled and not confi gured as a master, it will operate as a spi slave. as a slave, bytes are shifted in through the mosi pin a nd out through the miso pin by a ma ster device controlling the sck sig- nal. a bit counter in the spi0 logic counts sck edges . when 8 bits have been shifted through the shift reg- ister, the spif flag is set to logic 1, and the byte is copied into the receive buffer. data is read from the receive buffer by reading spi0dat. a slave device cannot initiate transfers. data to be transferred to the master device is pre-loaded into the shift register by writing to spi0dat. writes to spi0dat are double- buffered, and are placed in the transmit buffer first. if the shift register is empty, the contents of the transmit buffer will immediately be transferred into the shift register. when the sh ift register already contains data, the spi will wait until the byte is transferred before loading it with the transmit buffer?s contents. when configured as a slave, spi0 can be configured for 4-wire or 3-wire operation. the default, 4-wire slave mode, is active when nssmd1 (spi0cn.3) = 0 and nssmd0 (spi0cn.2) = 1. in 4-wire mode, the nss signal is routed to a port pin and configured as a digital input. spi0 is enabl ed when nss is logic 0, and disabled when nss is logic 1. the bit counter is reset on a falling edge of n ss. note that the nss sig- nal must be driven low at least 2 system clocks before the first active edge of sck for each byte transfer. figure 20.4 shows a connection diagram between tw o slave devices in 4-wire slave mode and a master device. 3-wire slave mode is active when nssmd1 (spi0cn. 3) = 0 and nssmd0 (spi0cn.2) = 0. nss is not used in this mode, and does not get mapped to an external port pin through the crossbar. since there is no way of uniquely addressing the device in 3-wire sl ave mode, spi0 must be the only slave device present on the bus. it is important to note that in 3-wire slav e mode there is no external means of resetting the bit counter that determines when a full byte has been received. the bit counter can only be reset by disabling and re-enabling spi0 with the spien bit. figure 20.3 shows a connection diagram between a slave device in 3-wire slave mode and a master device. 20.4. spi0 interrupt sources when spi0 interrupts are e nabled, the following four flags will gener ate an interrupt when they are set to logic 1: note: all of the following interrupt bits must be cleared by software. 1. the spi interrupt flag, spif (spi0cn.7) is set to logi c 1 at the end of each byte transfer. this flag can occur in all spi0 modes. 2. the write collision flag, wcol (spi0cn.6) is set to logic 1 if a write to spi0dat is attempted when the transmit buffer has not been emptied to the spi shift register. when this occurs, the write to spi0dat will be ignored, and the transmi t buffer will not be written.this flag can occur in all spi0 modes. 3. the mode fault flag modf (spi0cn.5) is set to logic 1 when spi0 is configured as a master, a nd for multi-master mode and the nss pin is pulled low. when a mode fault occurs, the msten and spien bits in spi0cn are set to logi c 0 to disable spi0 and allow another master device to access the bus. 4. the receive overrun flag rxovrn (spi0cn.4) is se t to logic 1 when configured as a slave, and a transfer is completed and the receive buffer still holds an unread byte from a previous transfer. the new byte is not transferred to the receive buffer, allowing the previously received data byte to be read. the data byte which caused the overrun is lost. c8051f040/1/2/3/4/5/6/7 260 rev. 1.5 20.5. serial clock timing as shown in figure 20.5, four combinations of serial clock phase and polarity can be selected using the clock control bits in the spi0 configuration register (spi0cfg). the ckpha bit (spi0cfg.5) selects one of two clock phases (edge used to latch the data). the ckpol bit (spi0cfg.4) selects between an active- high or active-low clock. both master and slave devi ces must be configured to use the same clock phase and polarity. note: spi0 should be disabled (by cleari ng the spien bit, spi0cn.0) when changing the clock phase or polarity. note that in master mode, the spi samples miso one system clock before the in active edge of sck (the edge where mosi changes state) to provide maximum settling time for the slave device. the spi0 clock rate register (spi0c kr) as shown in sfr definition 20.3 controls the master mode serial clock frequency. this register is ignored when operating in slave mode. when the spi is configured as a master, the maximum data transfer rate (bits/sec) is one-half the system clock frequency. when the spi is configured as a slave, the ma ximum data transfer rate (bits/sec) for full-duplex operation is 1/10 the system clock frequency, provided that the master iss ues sck, nss (in 4-wire slave mode), and the serial input data synchronously with the syst em clock. if the master issues sc k, nss, and the serial input data asynchronously, the maximum data transfer rate (bits/ sec) must be less than 1/10 the system clock fre- quency. in the special case where the master only wants to transmit data to the slave and does not need to receive data from the slave (i.e. half-duplex operati on), the spi slave can receive data at a maximum data transfer rate (bits/sec) of 1/4 the system clock frequency. this is provided that the master issues sck, nss, and the serial input data synchronously with the system clock. figure 20.5. data/clock timing diagram sck (ckpol=0, ckpha=0) sck (ckpol=0, ckpha=1) sck (ckpol=1, ckpha=0) sck (ckpol=1, ckpha=1) msb bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 miso/mosi nss c8051f040/1/2/3/4/5/6/7 rev. 1.5 261 20.6. spi special function registers spi0 is accessed and controlled through four special function registers in the system controller: spi0cn control register, spi0dat data re gister, spi0cfg configuration register, and spi0ckr clock rate register. the four special function registers related to the operation of the spi0 bus are described in the following definitions. sfr definition 20.1. spi0cfg: spi0 configuration bit 7: spibsy: spi busy. this bit is set to logic 1 when a spi transf er is in progress (master or slave mode). bit 6: msten: master mode enable. 0: disable master mode. operate in slave mode. 1: enable master mode. operate as a master. bit 5: ckpha: spi0 clock phase. this bit controls the spi0 clock phase. 0: data sampled on first edge of sck period. 1: data sampled on second edge of sck period. bit 4: ckpol: spi0 clock polarity. this bit controls the spi0 clock polarity. 0: sck line low in idle state. 1: sck line high in idle state. bit 3: slvsel: slave selected flag. this bit is set to logic 1 whenever the nss pin is low indicating spi0 is the selected slave. it is cleared to logic 0 when nss is high (slave not selected). this bit does not indicate the instantaneous value at the nss pin, but ra ther a de-glitched version of the pin input. bit 2: nssin: nss instantaneous pin input. this bit mimics the instantaneous value that is present on the nss port pin at the time that the register is read. this input is not de-glitched. bit 1: srmt: shift register empty (valid in slave mode). this bit will be set to logic 1 when all data has been transferred in/out of the shift register, and there is no new information available to read from the transmit buffer or write to the receive buffer. it returns to logic 0 when a data byte is transferred to the shift register from the transmit buffer or by a transition on sck. note: srmt = 1 when in master mode. bit 0: rxbmt: receive buffer empty (valid in slave mode). this bit will be set to logic 1 when the receiv e buffer has be en read and contains no new information. if there is new information available in the receive buffer that has not been read, this bit will return to logic 0. note: rxbmt = 1 when in master mode. r r/w r/w r/w r r r r reset value spibsy msten ckpha ckpol slvsel nssin srmt rxbmt 00000111 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: sfr page: 0x9a 0 c8051f040/1/2/3/4/5/6/7 262 rev. 1.5 sfr definition 20.2. spi0cn: spi0 control bit 7: spif: spi0 interrupt flag. this bit is set to logic 1 by hardware at the end of a data trans fer. if interrupts are enabled, setting this bit causes the cpu to vector to the spi0 interrupt service routine. this bit is not automatically cleared by hardware. it must be cleared by software. bit 6: wcol: write collision flag. this bit is set to logic 1 by hardware (and gene rates a spi0 interrupt) to indicate a write to the spi0 data register was attempted while a da ta transfer was in progress. it must be cleared by software. bit 5: modf: mode fault flag. this bit is set to logic 1 by hardware (and ge nerates a spi0 interrupt) when a master mode collision is detected (nss is low, msten = 1, and nssmd[1:0] = 01). this bit is not auto- matically cleared by hardware. it must be cleared by software. bit 4: rxovrn: receive overru n flag (slave mode only). this bit is set to logic 1 by hardware (and generates a spi0 interrupt) when the receive buffer still holds unread data from a previous tr ansfer and the last bit of the current transfer is shifted into the spi0 shift register. this bi t is not automatically cleared by hardware. it must be cleared by software. bits 3-2: nssmd1-nssmd0 : slave select mode. selects between the following nss operation modes: (see section ?20.2. spi0 master mode operation? on page 257 and section ?20.3. spi0 slave mode operation? on page 259 ). 00: 3-wire slave or 3-wire master mode. nss signal is not routed to a port pin. 01: 4-wire slave or multi-master mode (defau lt). nss is always an input to the device. 1x: 4-wire single-master mode. nss signal is mapped as an ou tput from the device and will assume the value of nssmd0. bit 1: txbmt: transmit buffer empty. this bit will be set to logic 0 when new data ha s been written to the transmit buffer. when data in the transmit buffer is tr ansferred to the spi sh ift register, this bit will be set to logic 1, indicating that it is safe to writ e a new byte to the transmit buffer. bit 0: spien: spi0 enable. this bit enables/disables the spi. 0: spi disabled. 1: spi enabled. r/w r/w r/w r/w r/w r/w r r/w reset value spif wcol modf rxovrn nssmd1 nssmd0 txbmt spien 00000110 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 bit addressable sfr address: sfr page: 0xf8 0 c8051f040/1/2/3/4/5/6/7 rev. 1.5 263 sfr definition 20.3. spi0ckr: spi0 clock rate bits 7-0: scr7-scr0: spi0 clock rate these bits determine the frequency of the sck output when the spi0 module is configured for master mode operation. the sck clock frequ ency is a divided version of the system clock, and is given in the following equation, where sysclk is the system clock frequency and spi0ckr is the 8-bit value held in the spi0ckr register. for 0 <= spi0ckr <= 255 example: if sysclk = 2 mhz and spi0ckr = 0x04, r/w r/w r/w r/w r/w r/w r/w r/w reset value scr7 scr6 scr5 scr4 scr3 scr2 scr1 scr0 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: sfr page: 0x9d 0 f sck 2000000 241 + ?? ? f sck 200 khz = f sck sysclk 2 spi 0 ckr 1+ ?? ? c8051f040/1/2/3/4/5/6/7 264 rev. 1.5 sfr definition 20.4. spi0dat: spi0 data bits 7-0: spi0dat: spi0 transmit and receive data. the spi0dat register is used to transmit an d receive spi0 data. writing data to spi0dat places the data into the transmit buffer and initiates a transfer when in master mode. a read of spi0dat returns the contents of the receive buffer. r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: sfr page: 0x9b 0 c8051f040/1/2/3/4/5/6/7 rev. 1.5 265 21. uart0 uart0 is an enhanced serial port with frame error detection and address recognition hardware. uart0 may operate in full-duplex asynchronous or half-d uplex synchronous modes, and mutiproccessor commu- nication is fully supported. receive data is buffered in a holding register, allowing uart0 to start reception of a second incoming data byte before software has finished reading the previ ous data byte. a receive overrun bit indicates when new received data is latc hed into the receive buffer before the previously received byte has been read. uart0 is accessed via its associated sfrs, serial c ontrol (scon0) and serial data buffer (sbuf0). the single sbuf0 location provides access to both tr ansmit and receive registers. reading scon0 accesses the receive register and writing scon0 accesses the transmit register. uart0 may be operated in polled or interrupt mode. uart0 has two sources of interrupts: a transmit interrupt flag, ti0 (scon0.1 ) set when transmission of a data byte is complete, and a receive interrupt flag, ri0 (scon0.0) set when reception of a data byte is complete. uart0 interrupt flags are not cleared by hardware when the cpu vectors to the interrupt service routine; they must be cleared manually by soft- ware. this allows software to determine the cause of the uart0 in terrupt (transmit complete or receive complete). figure 21.1. uart0 block diagram tx control tx clock tx irq zero detector send shift set qd clr stop bit gen. tb80 start data write to sbuf0 crossbar tx0 port i/o serial port (uart0) interrupt rx control start rx clock load sbuf 0x1ff shift en rx irq uart0 baud rate generation logic sfr bus input shift register (9 bits) frame error detection sbuf0 read sbuf0 sfr bus saddr0 saden0 match detect rb80 load sbuf0 crossbar rx0 sbuf0 address match scon0 s m 2 0 t b 8 0 r b 8 0 t i 0 r i 0 s m 1 0 s m 0 0 r e n 0 ssta0 t x c o l 0 s 0 t c l k 1 s 0 t c l k 1 s 0 r c l k 1 s 0 r c l k 1 r x o v 0 f e 0 s m o d 0 ti0 ri0 c8051f040/1/2/3/4/5/6/7 266 rev. 1.5 21.1. uart0 operational modes uart0 provides four operating modes (one synchronous and three asynchronous) selected by setting configuration bits in the scon0 register. these four modes offer different baud rates and communication protocols. the four modes are summarized in table 21.1. 21.1.1. mode 0: synchronous mode mode 0 provides synchronous, half-duplex communicati on. serial data is transmitted and received on the rx0 pin. the tx0 pin provides the shift clock for both transmit and receive. the mcu must be the master since it generates the shift clock for transmission in both directions (see the interconnect diagram in figure 21.3). data transmission begins when an instruction writes a data byte to the sbuf0 register. eight data bits are transferred lsb first (see the timing diagram in figure 21.2), and the ti0 transmit interrupt flag (scon0.1) is set at the end of the eighth bit time. data reception begins when the ren0 receive enable bit (scon0.4) is set to logic 1 and the ri0 receive in terrupt flag (scon0.0) is cleared. one cycle after the eighth bit is shifted in, the ri0 flag is set and rece ption stops until software clears the ri0 bit. an inter- rupt will occur if enabled when either ti0 or ri0 are set. the mode 0 baud rate is sysclk/12. rx0 is forced to open -drain in mode 0, and an external pullup will typically be required. figure 21.2. uart0 mode 0 timing diagram table 21.1. uart0 modes mode synchronization baud clock data bits start/stop bits 0 synchronous sysclk / 12 8 none 1 asynchronous timer 1, 2, 3, or 4 overflow 8 1 start, 1 stop 2 asynchronous sysclk / 32 or sysclk / 64 9 1 start, 1 stop 3 asynchronous timer 1, 2, 3, or 4 overflow 9 1 start, 1 stop d1 d0 d2 d3 d4 d5 d6 d7 rx (data out) mode 0 transmit d0 mode 0 receive rx (data in) d1 d2 d3 d4 d5 d6 d7 tx (clk out) tx (clk out) shift reg. clk c8051fxxx rx tx data 8 extra outputs c8051f040/1/2/3/4/5/6/7 rev. 1.5 267 figure 21.3. uart0 mode 0 interconnect 21.1.2. mode 1: 8-bit uart, variable baud rate mode 1 provides standard asynchronous, full-duplex communication using a total of 10 bits per data byte: one start bit, eight data bits (lsb first), and one stop bit. data are transmitted from the tx0 pin and received at the rx0 pin. on receive, the eight data bi ts are stored in sbuf0 and the stop bit goes into rb80 (scon0.2). data transmission begins when an instruction writes a data byte to the sbuf0 register. the ti0 transmit interrupt flag (scon0.1) is set at the end of the tran smission (the beginning of the stop-bit time). data reception can begin any time after the ren0 receive enab le bit (scon0.4) is set to logic 1. after the stop bit is received, the data byte will be loaded into the sbuf0 receive register if the following conditions are met: ri0 must be logic 0, and if sm20 is logic 1, the stop bit must be logic 1. if these conditions are met, the eight bits of data is stor ed in sbuf0, the stop bit is stored in rb80 and the ri0 flag is set. if these conditio ns are not met, sbuf0 and rb80 will no t be loaded and the ri0 flag will not be set. an interrupt will occur if enabled when ei ther ti0 or ri0 are set. figure 21.4. uart0 mode 1 timing diagram the baud rate generated in mode 1 is a function of timer overflow, shown in equation 21.1 and equation 21.3. uart0 can use timer 1 operating in 8-bit auto-reload mode , or timer 2, 3, or 4 operating in auto-reload mode to generate the baud rate (note that the tx and rx clocks are selected separately). on each timer overflow event (a rollover from all ones?0xff for timer 1, 0xffff for timers 2, 3 and 4? to zero) a clock is sent to the baud rate logic. timers 1, 2, 3, and 4 are selected as the baud rate source with bits in the ssta0 register (see sfr defini- tion 21.2). the transmit baud rate clock is selected using the s0tclk1 and s0tclk0 bits, and the receive baud rate clock is selected using the s0rclk1 and s0rclk0 bits. the mode 1 baud rate equations are shown below, wher e t1m is bit4 of register ckcon, th1 is the 8-bit reload register for timer 1, and [rcapnh, rcapnl] is the 16-bit reload register for timer 2, 3, or 4. equation 21.1. mode 1 baud rate using timer 1 the timer 1 overflow rate is determined by the timer 1 clock source (t1clk) and reload value (th1). the frequency of t1clk is selected as described in section ?23.1. timer 0 and timer 1? on page 287 . the timer 1 overflow rate is calculated as shown in equation 21.2. d1 d0 d2 d3 d4 d5 d6 d7 start bit mark stop bit bit times bit sampling space mode1_baudrate 1 32 ? timer1_overflowrate ? = when smod0 = 0: mode1_baudrate 1 16 ? timer1_overflowrate ? = when smod0 = 1: c8051f040/1/2/3/4/5/6/7 268 rev. 1.5 equation 21.2. timer 1 overflow rate when timers 2, 3, or 4 are selected as a baud ra te source, the baud rate is generated as shown in equation 21.3. equation 21.3. mode 1 baud rate usin g t imer 2, 3, or 4 the overflow rate for timer 2, 3, or 4 is determin ed by the clock source for the timer (tnclk) and the 16- bit reload value stored in the rcapn register (n = 2, 3, or 4), as shown in equation 21.4. equation 21.4. timer 2, 3, or 4 overflow rate timer1_overflowrate t1clk 256 th1 ? ?? ? = mode1_baudrate 1 16 ? timer234_overflowrate ? ?? = timer234_overflowrate tnclk 65536 rcapn? ?? ? = c8051f040/1/2/3/4/5/6/7 rev. 1.5 269 21.1.3. mode 2: 9-bit uart, fixed baud rate mode 2 provides asynchronous, full-duplex communicatio n using a total of eleven bits per data byte: a start bit, 8 data bits (lsb first), a programmable ninth da ta bit, and a stop bit. mode 2 supports multiprocessor communications and hardware address recognition (see section 21.2 ). on transmit, the ninth data bit is determined by the value in tb80 (scon0.3). it can be assigned the value of the parity flag p in the psw or used in multiprocessor communications. on receive, the ninth data bit goes into rb80 (scon0.2) and the stop bit is ignored. data transmission begins when an instruction writes a data byte to the sbuf0 register. the ti0 transmit interrupt flag (scon0.1) is set at the end of the tran smission (the beginning of the stop-bit time). data reception can begin any time after the ren0 receive enab le bit (scon0.4) is set to logic 1. after the stop bit is received, the data byte will be loaded into the sbuf0 re ceive register if ri0 is logic 0 and one of the following requirements are met: ? sm20 is logic 0 ? sm20 is logic 1, the received 9th bit is logic 1, and the received address matches the uart0 address as described in section 21.2 . if the above conditions are satisfied, the eight bits of dat a are stored in sbuf0, the ninth bit is stored in rb80 and the ri0 flag is set. if these conditions are not met, sbuf0 and rb80 will not be loaded and the ri0 flag will not be set. an in terrupt will occur if enabled when either ti0 or ri0 are set. the baud rate in mode 2 is either sysclk / 32 or sysclk / 64, according to the value of the smod0 bit in register ssta0. equation 21.5. mode 2 baud rate figure 21.5. uart0 mod es 2 and 3 t iming diagram figure 21.6. uart0 m odes 1, 2, and 3 in terco nnect diagram baudrate 2 smod0 sysclk 64 --------------------- - ?? ?? ? = d1 d0 d2 d3 d4 d5 d6 d7 start bit mark stop bit bit times bit sampling space d8 or rs-232 c8051fxxx rs-232 level xltr tx rx c8051fxxx rx tx mcu rx tx c8051f040/1/2/3/4/5/6/7 270 rev. 1.5 21.1.4. mode 3: 9-bit uart, variable baud rate mode 3 uses the mode 2 transmissi on protocol with the mode 1 baud rate generation. mode 3 operation transmits 11 bits: a start bit, 8 data bits (lsb first), a programmable ninth data bit, and a stop bit. the baud rate is derived from timer 1 or timer 2, 3, or 4 over flows, as defined by equation 21.1 and equation 21.3. multiprocessor communications and hardware addre ss recognition are supported, as described in section 21.2 . 21.2. multiprocessor communications modes 2 and 3 support multiprocessor communication between a master processor and one or more slave processors by special use of the ninth data bit and the built-in uart0 address recognition hardware. when a master processor wants to transmit to one or more sl aves, it first sends an address byte to select the tar- get(s). an address byte differs from a data byte in that its ninth bit is logic 1; in a data byte, the ninth bit is always set to logic 0. uart0 will recognize as ?v alid? (i.e., capable of causing an interrupt) two types of addresses: (1) a masked address and (2) a broadcast address at any given time . both are described below. c8051f040/1/2/3/4/5/6/7 rev. 1.5 271 21.3. configuration of a masked address the uart0 address is configured via two sfrs: saddr0 (serial address) and saden0 (serial address enable). saden0 sets the bit mask for the address he ld in saddr0: bits set to logic 1 in saden0 corre- spond to bits in saddr0 that are checked against the received address byte; bits set to logic 0 in saden0 correspond to ?don?t care? bits in saddr0. setting the sm20 bit (sco n0.5) configures uar t0 such that when a stop bit is received, uart0 will gen- erate an interrupt only if the ninth bit is logic 1 (rb8 0 = ?1?) and the received data byte matches the uart0 slave address. following th e received address interr upt, the slave will clear it s sm20 bit to enable inter- rupts on the reception of the following data byte(s). once the entire message is received, the addressed slave resets its sm20 bit to ignore all transmissions until it receives the next address byte. while sm20 is logic 1, uart0 ignores all bytes that do not match th e uart0 address and include a ninth bit that is logic 1. 21.4. broadcast addressing multiple addresses can be assigned to a single sl ave and/or a single address can be assigned to multiple slaves, thereby enabling "broadcast" transmissions to more than one slave simultaneously. the broadcast address is the logical or of registers saddr0 and saden0, and ?0?s of the result are treated as ?don?t cares?. typically a broadcast address of 0xff (hexad ecimal) is acknowledged by all slaves, assuming ?don?t care? bits as ?1?s. the master processor can be configured to receive all transmissions or a protocol can be implemented such that the master/slave role is temporarily reversed to enable half-duplex trans- mission between the original master and slave(s). note in the above examples 4, 5, and 6, each slave wo uld recognize as ?valid? an address of 0xff as a broadcast address. also note that examples 4, 5, and 6 uses t he same saddr0 and saden0 register values as shown in the examples 1, 2, and 3 respectively (slaves #1, 2, and 3). thus, a master could address each slave device individually using a masked address, and also broadcast to all three slave devices. for example, if a master were to send an address ?11110101?, only slave #1 would recognize the address as valid. if a master were to then send an address of ?11111111?, all three slave devices would rec- ognize the address as a valid broadcast address. example 1, slave #1 example 2, slave #2 example 3, slave #3 saddr0 = 00110101 saddr0 = 00110101 saddr0 = 00110101 saden0 = 00001111 saden0 = 11110011 saden0 = 11000000 uart0 address = xxxx0101 uart0 address = 0011xx01 uart0 address = 00xxxxxx example 4, slave #1 example 5, slave #2 example 6, slave #3 saddr0 = 00110101 saddr0 = 00110101 saddr0 = 00110101 saden0 = 00001111 saden0 = 11110011 saden0 = 11000000 broadcast address = 00111111 broadcast address = 11110111 broadcast address = 11110101 where all zeroes in the broadcast address are don?t cares. c8051f040/1/2/3/4/5/6/7 272 rev. 1.5 figure 21.7. uart multi-processor mode interconnect diagram 21.5. frame and transmi ssion error detection all modes: the transmit collision bit (txcol0 bit in register ssta0 ) reads '1' if user software writes data to the sbuf0 register while a tr ansmit is in progress. modes 1, 2, and 3: the receive overrun bit (rxov0 in register ssta0) reads '1 ' if a new data byte is latched into the receive buffer before software has read the previous byte. the frame error bit (fe0 in register ssta0) reads '1' if an invalid (low) stop bit is detected. master device slave device tx rx rx tx slave device rx tx slave device rx tx +5v c8051f040/1/2/3/4/5/6/7 rev. 1.5 273 table 21.2. oscillator frequencies for standard baud rates oscillator frequency (mhz) divide factor timer 1 reload va lue 1 timer 2, 3, or 4 reload v alue resulting baud rate (hz) 2 24.0 208 0xf3 0xfff3 115200 (115384) 22.1184 192 0xf4 0xfff4 115200 18.432 160 0xf6 0xfff6 115200 11.0592 96 0xfa 0xfffa 115200 3.6864 32 0xfe 0xfffe 115200 1.8432 16 0xff 0xffff 115200 24.0 832 0xcc 0xffcc 28800 (28846) 22.1184 768 0xd0 0xffd0 28800 18.432 640 0xd8 0xffd8 28800 11.0592 348 0xe8 0xffe8 28800 3.6864 128 0xf8 0xfff8 28800 1.8432 64 0xfc 0xfffc 28800 24.0 2496 0x64 0xff64 9600 (9615) 22.1184 2304 0x70 0xff70 9600 18.432 1920 0x88 0xff88 9600 11.0592 1152 0xb8 0xffb8 9600 3.6864 384 0xe8 0xffe8 9600 1.8432 192 0xf4 0xfff4 9600 notes: 1. assumes smod0 =1 and t1m=1. 2. nu mbers in parenthesis show the actual baud rate. c8051f040/1/2/3/4/5/6/7 274 rev. 1.5 sfr definition 21.1. scon0: uart0 control bits7-6: sm00-sm10: serial port operation mode: write: when written, these bits select the se rial port operation mode as follows: reading these bits returns the current uart0 mode as defined above. bit5: sm20: multiprocesso r communication enable. the function of this bit is dependen t on the serial port operation mode. mode 0: no effect mode 1: checks for valid stop bit. 0: logic level of stop bit is ignored. 1: ri0 will only be activated if stop bit is logic level 1. mode 2 and 3: multiprocessor communications enable. 0: logic level of ninth bit is ignored. 1: ri0 is set and an interrupt is generated only when the ninth bit is logic 1 and the received address matches the uart0 address or the broadcast address. bit4: ren0: receive enable. this bit enables/disables the uart0 receiver. 0: uart0 reception disabled. 1: uart0 reception enabled. bit3: tb80: ninth transmission bit. the logic level of this bit will be assigned to the ninth transmission bit in modes 2 and 3. it is not used in modes 0 and 1. set or cleared by software as required. bit2: rb80: ninth receive bit. the bit is assigned the logic level of the ninth bit received in modes 2 and 3. in mode 1, if sm20 is logic 0, rb80 is assigned the logic leve l of the received stop bit. rb8 is not used in mode 0. bit1: ti0: transmit interrupt flag. set by hardware when a byte of data has been transmitted by uart0 (after the 8th bit in mode 0, or at the beginning of the stop bit in other modes). when the uart0 interrupt is enabled, setting this bit causes the cpu to ve ctor to the uart0 inte rrupt service routine. this bit must be cleared manually by software. bit0: ri0: receive interrupt flag. set by hardware when a byte of data has been received by uart0 (as selected by the sm20 bit). when the uart0 interrupt is enabled, setting this bit causes the cpu to vector to the uart0 interrupt service routine. this bi t must be cleared manually by software. r/w r/w r/w r/w r/w r/w r/w r/w reset value sm00 sm10 sm20 ren0 tb80 rb80 ti0 ri0 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: sfr page: 0x98 0 sm00 sm10 mode 0 0 mode 0: synchronous mode 0 1 mode 1: 8-bit uart, variable baud rate 1 0 mode 2: 9-bit uart, fixed baud rate 1 1 mode 3: 9-bit uart, variable baud rate c8051f040/1/2/3/4/5/6/7 rev. 1.5 275 sfr definition 21.2. ssta0: uart0 status and clock selection bit7: fe0: frame error flag. this flag indicates if an inva lid (low) stop bit is detected. 0: frame error has not been detected 1: frame error has been detected. bit6: rxov0: receive overrun flag. this flag indicates new data has been latched into the receive buffer before software has read the previous byte. 0: receive overrun has not been detected. 1: receive overrun has been detected. bit5: txcol0: transmit collision flag. this flag indicates user software has written to the sbuf0 register while a transmission is in progress. 0: transmission collisio n has not been detected. 1: transmission collisio n has been detected. bit4: smod0: uart0 baud rate doubler enable. this bit enables/disables the divide-by-two fu nction of the uart0 baud rate logic for config- urations described in the uart0 section. 0: uart0 baud rate divide-by-two enabled. 1: uart0 baud rate divide-by-two disabled. bits3-2: uart0 transmit baud rate clock selection bits. bits1-0: uart0 receive baud rate clock selection bits r/w r/w r/w r/w r/w r/w r/w r/w reset value fe0 rxov0 txcol0 smod0 s0tclk1 s0tclk0 s0rclk1 s0rclk0 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: sfr page: 0x91 0 s0tclk1 s0tclk0 serial transmit baud rate clock source 0 0 timer 1 generates uart0 tx baud rate 0 1 timer 2 overflow generates uart0 tx baud rate 1 0 timer 3 overflow generates uart0 tx baud rate 1 1 timer 4 overflow generates uart0 tx baud rate s0rclk1 s0rclk0 serial receive baud rate clock source 0 0 timer 1 generates uart0 rx baud rate 0 1 timer 2 overflow generates uart0 rx baud rate 1 0 timer 3 overflow generates uart0 rx baud rate 1 1 timer 4 overflow generates uart0 rx baud rate c8051f040/1/2/3/4/5/6/7 276 rev. 1.5 sfr definition 21.3. sbuf0: uart0 data buffer sfr definition 21.4. saddr0: uart0 slave address sfr definition 21.5. saden0: uart0 slave address enable bits7-0: sbuf0.[7:0]: uart0 buffer bits 7-0 (msb-lsb) this is actually two registers; a transmit and a receive buffer register. when data is moved to sbuf0, it goes to the transmit buffer and is held for serial transmission. moving a byte to sbuf0 is what initiates the transmission. when data is moved from sbuf0, it comes from the receive buffer. r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: sfr page: 0x99 0 bits7-0: saddr0.[7:0]: uart0 slave address the contents of this register are used to define the uart0 slave address. register saden0 is a bit mask to determine which bits of sa ddr0 are checked against a received address: corresponding bits set to logic 1 in saden0 are checked; corresponding bits set to logic 0 are ?don?t cares?. r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: sfr page: 0xa9 0 bits7-0: saden0.[7:0]: uart0 slave address enable bits in this register enable corresponding bits in register saddr0 to determine the uart0 slave address. 0: corresponding bit in saddr0 is a ?don?t care?. 1: corresponding bit in saddr0 is checked against a received address. r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: sfr page: 0xb9 0 c8051f040/1/2/3/4/5/6/7 rev. 1.5 277 22. uart1 uart1 is an asynchronous, full duplex serial port offering modes 1 and 3 of the standard 8051 uart. enhanced baud rate support allows a wide range of clock sources to generate standard baud rates (details in section ?22.1. enhanced baud rate generation? on page 278 ). received data buffering allows uart1 to start reception of a second incoming data byte before software has finished reading the previous data byte. uart1 has two associated sfrs: serial control regist er 1 (scon1) and serial data buffer 1 (sbuf1). the single sbuf1 location provides access to both transmit and receive registers. reading sbuf1 accesses the buffered receive re gister; writing sbuf1 access es the transmit register. with uart1 interrupts enabled, an interrupt is generated each time a transmit is completed (ti1 is set in scon1), or a data byte has been received (ri1 is set in scon1). the uart1 interrupt flags are not cleared by hardware when the cpu vectors to the interr upt service routine. they must be cleared manually by software, allowing software to determine the cause of the uart1 interrupt (transmit complete or receive complete). figure 22.1. uart1 block diagram uart1 baud rate generator ri1 scon1 ri1 ti1 rb81 tb81 ren1 mce1 s1mode tx control tx clock send sbuf1 (tx shift) start data write to sbuf1 crossbar tx1 shift zero detector tx irq set qd clr stop bit tb81 sfr bus serial port interrupt ti1 port i/o rx control start rx clock load sbuf1 shift 0x1ff rb81 rx irq input shift register (9 bits) load sbuf1 read sbuf1 sfr bus crossbar rx1 sbuf1 (rx latch) c8051f040/1/2/3/4/5/6/7 278 rev. 1.5 22.1. enhanced baud rate generation the uart1 baud rate is generated by timer 1 in 8-bit auto-reload mode. the tx clock is generated by tl1; the rx clock is generated by a copy of tl1 (shown as rx timer in figure 22.2), which is not user- accessible. both tx and rx timer overflows are divid ed by two to generate the tx and rx baud rates. the rx timer runs when timer 1 is enabled, and uses the same reload value (th1). however, an rx timer reload is forced when a start condition is detected on the rx pin. this allows a receive to begin any time a start is detected, independent of the tx timer state. figure 22.2. uart1 baud rate logic timer 1 should be configured for mode 2, 8-bit auto-reload (see section ?23.1.3. mode 2: 8-bit counter/ timer with auto-reload? on page 289 ). the timer 1 reload value shou ld be set so that overflows will occur at two times the desired baud rate. note that timer 1 may be clocked by one of five sources: sys- clk, sysclk / 4, sysclk / 12, sysclk / 48, or the ex ternal oscillator clock / 8. for any given timer 1 clock source, the uart1 baud rate is determined by equation 22.1, where t1 clk is the frequency of the clock supplied to timer 1, and th1 is the high byte of timer 1 (reload value). equation 22.1. uart1 baud rate ? timer 1 clock frequency is selected as described in section ?23.1. timer 0 and timer 1? on page 287 . a quick reference for typical baud rates and system cl ock frequencies is given in table 22.1 through table 22.6. note that the internal oscillator may still generate the system clock when the external oscillator is driving timer 1 (see section ?23.1. timer 0 and timer 1? on page 287 for more details). rx timer start detected overflow overflow th1 tl1 tx clock 2 rx clock 2 timer 1 uart1 uartbaudrate t 1 clk 256 th 1? ?? ? c8051f040/1/2/3/4/5/6/7 rev. 1.5 279 22.2. operational modes uart1 provides standard asynchronous, full duplex communication. the uart mode (8-bit or 9-bit) is selected by the s1mode bit (scon1.7). typical uart connection options are shown below. figure 22.3. uart interconnect diagram 22.2.1. 8-bit uart 8-bit uart mode uses a total of 10 bits per data byte: one start bit, eight data bits (lsb first), and one stop bit. data are transmitted lsb first from the tx1 pin a nd received at the rx1 pin. on receive, the eight data bits are stored in sbuf1 and the stop bit goes into rb81 (scon1.2). data transmission begins wh en software writes a data byte to th e sbuf1 register. the ti1 transmit inter- rupt flag (scon1.1) is set at the end of the transmi ssion (the beginning of the st op-bit time). data recep- tion can begin any time after the ren1 receive enable bi t (scon1.4) is set to logic 1. after the stop bit is received, the data byte w ill be loaded into the sbuf1 re ceive register if the follo wing conditions are met: ri1 must be logic 0, and if mce1 is logic 1, the stop bi t must be logic 1. in the event of a receive data over- run, the first received 8 bits are latched into the sbu f1 receive register and the following overrun data bits are lost. if these conditions are met, the eight bits of data is stor ed in sbuf1, the stop bit is stored in rb81 and the ri1 flag is set. if these conditio ns are not met, sbuf1 and rb81 will no t be loaded and the ri1 flag will not be set. an interrupt will occur if enabled when ei ther ti1 or ri1 is set. figure 22.4. 8-bit u art timing diagram or rs-232 c8051fxxx rs-232 level xltr tx rx c8051fxxx rx tx mcu rx tx d1 d0 d2 d3 d4 d5 d6 d7 start bit mark stop bit bit times bit sampling space c8051f040/1/2/3/4/5/6/7 280 rev. 1.5 22.2.2. 9-bit uart 9-bit uart mode uses a total of eleven bits per data byte: a start bit, 8 data bits (lsb first), a programma- ble ninth data bit, and a stop bit. the state of the nint h transmit data bit is determ ined by the value in tb81 (scon1.3), which is assigned by user software. it can be assigned the value of the parity flag (bit p in reg- ister psw) for error detection, or used in multiprocessor communications. on receive, the ninth data bit goes into rb81 (scon1.2) and the stop bit is ignored. data transmission begins when an instruction writes a data byte to the sbuf1 register. the ti1 transmit interrupt flag (scon1.1) is set at the end of the tran smission (the beginning of the stop-bit time). data reception can begin any time after the ren1 receive en able bit (scon1.4) is set to ?1?. after the stop bit is received, the data byte will be lo aded into the sbuf1 receive register if the followin g conditions are met: (1) ri1 must be logic 0, and (2) if mce1 is logic 1, the 9th bit must be logic 1 (when mce1 is logic 0, the state of the ninth data bit is unimportant). if these cond itions are met, the eight bits of data are stored in sbuf1, the ninth bit is stored in rb81, and the ri1 flag is set to ?1?. if the above conditions are not met, sbuf1 and rb81 will not be loaded and the ri1 flag will not be set to ?1?. a ua rt1 interrupt will occur if enabled when either ti1 or ri1 is set to ?1?. figure 22.5. 9-bit u art timing diagram d1 d0 d2 d3 d4 d5 d6 d7 start bit mark stop bit bit times bit sampling space d8 c8051f040/1/2/3/4/5/6/7 rev. 1.5 281 22.3. multiprocessor communications 9-bit uart mode supports multiprocessor communication between a master processor and one or more slave processors by special use of t he ninth data bit. when a master processor wants to transmit to one or more slaves, it first sends an address byte to select th e target(s). an address byte differs from a data byte in that its ninth bit is logic 1; in a data byte, the ninth bit is always set to logic 0. setting the mce1 bit (scon1.5) of a slave processor co nfigures its uart such that when a stop bit is received, the uart will generate an in terrupt only if the ninth bit is logic one (rb81 = 1) signifying an address byte has been received. in the uart interrupt handler, software should compare the received address with the slave's own assigned 8-bit address. if the addresses match, the slave should clear its mce1 bit to enable interrupts on the reception of the fo llowing data byte(s). slaves that weren't addressed leave their mce1 bits set and do not generate interrupts on the reception of the following data bytes, thereby ignoring the data. once the entire message is received, the addressed slave should reset its mce1 bit to ignore all transmissions until it receives the next address byte. multiple addresses can be assigned to a single sl ave and/or a single address can be assigned to multiple slaves, thereby enabling "broadcast" transmissions to more than one slave simultaneously. the master processor can be configured to receive all transmissi ons or a protocol can be implemented such that the master/slave role is tem porarily reversed to enable half-duplex transmission between the original master and slave(s). figure 22.6. uart multi-processor mode interconnect diagram master device slave device tx rx rx tx slave device rx tx slave device rx tx +5v c8051f040/1/2/3/4/5/6/7 282 rev. 1.5 sfr definition 22.1. scon1: serial port 1 control bit7: s1mode: serial port 1 operation mode. this bit selects the uart1 operation mode. 0: mode 0: 8-bit uart with variable baud rate 1: mode 1: 9-bit uart with variable baud rate bit6: unused. read = 1b . write = don?t care. bit5: mce1: multiprocessor communication enable. the function of this bit is dependent on the serial port 0 operation mode. mode 0: checks for valid stop bit. 0: logic level of stop bit is ignored. 1: ri1 will only be activated if stop bit is logic level 1. mode 1: multiprocessor communications enable. 0: logic level of ninth bit is ignored. 1: ri1 is set and an interrupt is generated only when the ninth bit is logic 1. bit4: ren1: receive enable. this bit enables/disables the uart receiver. 0: uart1 reception disabled. 1: uart1 reception enabled. bit3: tb81: ninth transmission bit. the logic level of this bit will be assigned to the ninth transmission bit in 9-bit uart mode. it is not used in 8-bit uart mode. set or cleared by software as required. bit2: rb81: ninth receive bit. rb81 is assigned the value of the stop bit in mode 0; it is assigned the value of the 9th data bit in mode 1. bit1: ti1: transmit interrupt flag. set by hardware when a byte of data has been transmitted by uart1 (after the 8th bit in 8- bit uart mode, or at the beginning of the stop bit in 9-bit uart mode). when the uart1 interrupt is enabled, setting this bit causes the cpu to vector to the uart1 interrupt service routine. this bit must be cleared manually by software. bit0: ri1: receive interrupt flag. set to ?1? by hardware when a byte of data ha s been received by uart1 (set at the stop bit sampling time). when the uart1 interrupt is enabled, setting this bit to ?1? causes the cpu to vector to the uart1 inte rrupt service routine. this bit must be cleared manually by software. r/wr/wr/wr/wr/wr/wr/w r/wreset value s1mode - mce1 ren1 tb81 rb81 ti1 ri1 01000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 bit addressable sfr address: sfr page: 0x98 1 c8051f040/1/2/3/4/5/6/7 rev. 1.5 283 sfr definition 22.2. sbuf1: serial (uart1 ) por t data buffer bits7-0: sbuf1[7:0]: serial data buffer bits 7-0 (msb-lsb) this sfr accesses two registers; a transmit shif t register and a receive latch register. when data is written to sbuf1, it goes to the transmit shift register and is he ld for serial transmis- sion. writing a byte to sbuf1 is what initiate s the transmission. a read of sbuf1 returns the contents of the receive latch. r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: sfr page: 0x99 1 c8051f040/1/2/3/4/5/6/7 284 rev. 1.5 table 22.1. timer settings for standard baud rates using the internal 24.5 mhz os cillator frequency: 24.5 mhz target baud rate (bps) baud rate % error oscillator divide factor timer clock source sca1-sca0 (pre-scale select) * t1m * timer 1 reload value (hex) sysclk from internal osc. 230400 -0.32% 106 sysclk xx 1 0xcb 115200 -0.32% 212 sysclk xx 1 0x96 57600 0.15% 426 sysclk xx 1 0x2b 28800 -0.32% 848 sysclk / 4 01 0 0x96 14400 0.15% 1704 sysclk / 12 00 0 0xb9 9600 -0.32% 2544 sysclk / 12 00 0 0x96 2400 -0.32% 10176 sysclk / 48 10 0 0x96 1200 0.15% 20448 sysc lk / 48 10 0 0x2b x = don?t care *note: sca1-sca0 and t1m bit definitions can be found in section 23.1 . table 22.2. timer settings for standard baud rates using an external 25.0 mhz os cillator frequency: 25.0 mhz target baud rate (bps) baud rate % error oscillator divide factor timer clock source sca1-sca0 (pre-scale select) * t1m * timer 1 reload value (hex) sysclk from external osc. 230400 -0.47% 108 sysclk xx 1 0xca 115200 0.45% 218 sysclk xx 1 0x93 57600 -0.01% 434 sysclk xx 1 0x27 28800 0.45% 872 sysclk / 4 01 0 0x93 14400 -0.01% 1736 sysclk / 4 01 0 0x27 9600 0.15% 2608 extclk / 8 11 0 0x5d 2400 0.45% 10464 sysclk / 48 10 0 0x93 1200 -0.01% 20832 sysc lk / 48 10 0 0x27 sysclk from internal osc. 57600 -0.47% 432 extclk / 8 11 0 0xe5 28800 -0.47% 864 extclk / 8 11 0 0xca 14400 0.45% 1744 extclk / 8 11 0 0x93 9600 0.15% 2608 extclk / 8 11 0 0x5d x = don?t care *note: sca1-sca0 and t1m bit definitions can be found in section 23.1 . c8051f040/1/2/3/4/5/6/7 rev. 1.5 285 table 22.3. timer settings for standard baud rates using an external 22.1 184 mhz oscillator frequency: 22.1184 mhz target baud rate (bps) baud rate % error oscillator divide factor timer clock source sca1-sca0 (pre-scale select) * t1m * timer 1 reload value (hex) sysclk from external osc. 230400 0.00% 96 sysclk xx 1 0xd0 115200 0.00% 192 sysclk xx 1 0xa0 57600 0.00% 384 sysclk xx 1 0x40 28800 0.00% 768 sysclk / 12 00 0 0xe0 14400 0.00% 1536 sysclk / 12 00 0 0xc0 9600 0.00% 2304 sysclk / 12 00 0 0xa0 2400 0.00% 9216 sysclk / 48 10 0 0xa0 1200 0.00% 18432 sysclk / 48 10 0 0x40 sysclk from internal osc. 230400 0.00% 96 extclk / 8 11 0 0xfa 115200 0.00% 192 extclk / 8 11 0 0xf4 57600 0.00% 384 extclk / 8 11 0 0xe8 28800 0.00% 768 extclk / 8 11 0 0xd0 14400 0.00% 1536 extclk / 8 11 0 0xa0 9600 0.00% 2304 extclk / 8 11 0 0x70 x = don?t care *note: sca1-sca0 and t1m bit definitions can be found in section 23.1 . table 22.4. timer settings for standard baud rates using an external 18.432 mhz os cillator frequency: 18.432 mhz target baud rate (bps) baud rate % error oscillator divide factor timer clock source sca1-sca0 (pre-scale select) * t1m * timer 1 reload value (hex) sysclk from external osc. 230400 0.00% 80 sysclk xx 1 0xd8 115200 0.00% 160 sysclk xx 1 0xb0 57600 0.00% 320 sysclk xx 1 0x60 28800 0.00% 640 sysclk / 4 01 0 0xb0 14400 0.00% 1280 sysclk / 4 01 0 0x60 9600 0.00% 1920 sysclk / 12 00 0 0xb0 2400 0.00% 7680 sysclk / 48 10 0 0xb0 1200 0.00% 15360 sysclk / 48 10 0 0x60 sysclk from internal osc. 230400 0.00% 80 extclk / 8 11 0 0xfb 115200 0.00% 160 extclk / 8 11 0 0xf6 57600 0.00% 320 extclk / 8 11 0 0xec 28800 0.00% 640 extclk / 8 11 0 0xd8 14400 0.00% 1280 extclk / 8 11 0 0xb0 9600 0.00% 1920 extclk / 8 11 0 0x88 c8051f040/1/2/3/4/5/6/7 286 rev. 1.5 x = don?t care *note: sca1-sca0 and t1m bit definitions can be found in section 23.1 . table 22.4. timer settings for standard baud rates using an ex ternal 18.432 mhz oscillator frequency: 18.432 mhz target baud rate (bps) baud rate % error oscillator divide factor timer clock source sca1-sca0 (pre-scale select) * t1m * timer 1 reload value (hex) c8051f040/1/2/3/4/5/6/7 rev. 1.5 287 table 22.5. timer settings for standard baud rates using an external 1 1.0592 mhz oscillator frequency: 11.0592 mhz target baud rate (bps) baud rate % error oscillator divide factor timer clock source sca1-sca0 (pre-scale select) * t1m * timer 1 reload value (hex) sysclk from external osc. 230400 0.00% 48 sysclk xx 1 0xe8 115200 0.00% 96 sysclk xx 1 0xd0 57600 0.00% 192 sysclk xx 1 0xa0 28800 0.00% 384 sysclk xx 1 0x40 14400 0.00% 768 sysclk / 12 00 0 0xe0 9600 0.00% 1152 sysclk / 12 00 0 0xd0 2400 0.00% 4608 sysclk / 12 00 0 0x40 1200 0.00% 9216 sysclk / 48 10 0 0xa0 sysclk from internal osc. 230400 0.00% 48 extclk / 8 11 0 0xfd 115200 0.00% 96 extclk / 8 11 0 0xfa 57600 0.00% 192 extclk / 8 11 0 0xf4 28800 0.00% 384 extclk / 8 11 0 0xe8 14400 0.00% 768 extclk / 8 11 0 0xd0 9600 0.00% 1152 extclk / 8 11 0 0xb8 x = don?t care *note: sca1-sca0 and t1m bit definitions can be found in section 23.1 . table 22.6. timer settings for standard ba ud rates using an external 3.6864 mhz os cillator frequency: 3.6864 mhz target baud rate (bps) baud rate % error oscillator divide factor timer clock source sca1-sca0 (pre-scale select) * t1m * timer 1 reload value (hex) sysclk from external osc. 230400 0.00% 16 sysclk xx 1 0xf8 115200 0.00% 32 sysclk xx 1 0xf0 57600 0.00% 64 sysclk xx 1 0xe0 28800 0.00% 128 sysclk xx 1 0xc0 14400 0.00% 256 sysclk xx 1 0x80 9600 0.00% 384 sysclk xx 1 0x40 2400 0.00% 1536 sysclk / 12 00 0 0xc0 1200 0.00% 3072 sysclk / 12 00 0 0x80 sysclk from internal osc. 230400 0.00% 16 extclk / 8 11 0 0xff 115200 0.00% 32 extclk / 8 11 0 0xfe 57600 0.00% 64 extclk / 8 11 0 0xfc 28800 0.00% 128 extclk / 8 11 0 0xf8 14400 0.00% 256 extclk / 8 11 0 0xf0 9600 0.00% 384 extclk / 8 11 0 0xe8 c8051f040/1/2/3/4/5/6/7 288 rev. 1.5 x = don?t care *note: sca1-sca0 and t1m bit definitions can be found in section 23.1 . table 22.6. timer settings for standard baud rates using an external 3.6864 mhz oscillator frequency: 3.6864 mhz target baud rate (bps) baud rate % error oscillator divide factor timer clock source sca1-sca0 (pre-scale select) * t1m * timer 1 reload value (hex) c8051f040/1/2/3/4/5/6/7 rev. 1.5 287 23. timers each mcu includes 5 counter/timers: timer 0 and timer 1 are 16-bit counter/timers compatible with those found in the standard 8051. timer 2, timer 3, and ti mer 4 are 16-bit auto-reload and capture counter/tim- ers for use with the adc, dac?s, square-wave generati on, or for general-purpose use. these timers can be used to measure time intervals, count external events and generate periodic interrupt requests. timer 0 and timer 1 are nearly identical and have four primary modes of operation. timers 2, 3, and 4 are identi- cal, and offer not only 16-bit auto -reload and capture, but have the ability to pr oduce a 50% duty-cycle square-wave (toggle output) at an external port pin. timers 0 and 1 may be clocked by one of five sources, deter mined by the timer mode select bits (t1m- t0m) and the clock scale bits (sca1-sca0). the cl ock scale bits define a pre-scaled clock by which timer 0 and/or timer 1 may be clocked (see sfr definition 23.3 for pre-scaled clock selection). timer 0/1 may then be configured to use this pre-scaled clock signal or the system clock. timers 2, 3, and 4 may be clocked by the system clock, the system clock divided by 12, or the external oscillator clock source divided by 8. timer 0 and timer 1 may also be operated as counte rs. when functioning as a counter, a counter/timer register is incremented on each high -to-low transition at the selected input pin. events with a frequency of up to one-fourth the system clock's frequency can be counted. th e input signal need not be periodic, but it should be held at a given logic level for at least two fu ll system clock cycles to ensu re the level is properly sampled. 23.1. timer 0 and timer 1 each timer is implemented as 16-bit register accessed as two separate bytes: a low byte (tl0 or tl1) and a high byte (th0 or th1). the counter/timer control register (tcon) is used to enable timer 0 and timer 1 as well as indicate their status. timer 0 interrupts can be enabled by setting the et0 bit in the ie register ( section ?12.3.5. interrupt register descriptions? on page 156 ); timer 1 interrupts can be enabled by setting the et1 bit in the ie register ( section 12.3.5 ). both counter/timers operate in one of four primary modes selected by setting the mode select bits t1m1-t0m0 in the counter/timer mode register (tmod). each timer can be configured independently. 23.1.1. mode 0: 13-bit counter/timer timer 0 and timer 1 operate as 13-bit counter/timers in mode 0. the following describes the configuration and operation of timer 0. however, both timers operat e identically, and timer 1 is configured in the same manner as described for timer 0. the th0 register holds the eight msbs of the 13-bit c ounter/timer. tl0 holds the five lsbs in bit positions tl0.4-tl0.0. the three upper bits of tl0 (tl0.7-tl0 .5) are indeterminate and should be masked out or ignored when reading. as the 13-bit timer register increments and overflows from 0x1fff (all ones) to 0x0000, the timer overflow flag tf 0 (tcon.5) is set and an interrupt will occur if timer 0 interrupts are enabled. timer 0 and timer 1 modes: timer 2, 3, and 4 modes: 13-bit counter/timer 16-bit c ounter/timer with auto-reload 16-bit counter/timer 16-bit counter/timer with capture 8-bit counter/timer with auto-reload toggle output two 8-bit counter/timers (timer 0 only) c8051f040/1/2/3/4/5/6/7 288 rev. 1.5 the c/t0 bit (tmod.2) selects the counter/timer's cloc k source. when c/t0 is set to logic 1, high-to-low transitions at the selected timer 0 input pin (t0) increment the timer register (refer to section ?17.1. ports 0 through 3 and the priority crossbar decoder? on page 204 for information on selecting and configuring external i/ o pins). clearing c/t0 selects the cloc k defined by the t0m bit (ckcon.3). when t0m is set, timer 0 is clocked by the system cl ock. when t0m is cleared, timer 0 is clocked by the source selected by the clock scale bits in ckco n (see sfr definition 23.3). setting the tr0 bit (tcon.4) enables the timer when ei ther gate0 (tmod.3) is logic 0 or the input signal /int0 is logic-level 1. setting gate0 to ?1? allows the timer to be controlled by the external input signal / int0 (see section ?12.3.5. interrupt register descriptions? on page 156 ), facilitating pulse width mea- surements. setting tr0 does not force the timer to reset. the timer registers should be loaded with the desired initial value before the timer is enabled. tl1 and th1 form the 13-bit register for timer 1 in the same manner as described above for tl0 and th0. timer 1 is configured and controlled using the relevant tcon and tmod bits just as with timer 0. the input signal /int1 is used with timer 1. figure 23.1. t0 mode 0 block diagram 23.1.2. mode 1: 16-bit counter/timer mode 1 operation is the same as mode 0, except that the counter/timer registers use all 16 bits. the coun- ter/timers are enabled and configured in mode 1 in the same manner as for mode 0. tr0 gate0 /int0 counter/timer 0 x x disabled 1 0 x enabled 110disabled 111enabled note: x = don't care tclk tl0 (5 bits) th0 (8 bits) tcon tf0 tr0 tr1 tf1 ie1 it1 ie0 it0 interrupt tr0 0 1 0 1 sysclk pre-scaled clock ckcon s c a 0 s c a 1 t 1 m t 0 m tmod t 1 m 1 t 1 m 0 c / t 1 g a t e 1 g a t e 0 c / t 0 t 0 m 1 t 0 m 0 gate0 /int0 t0 crossbar c8051f040/1/2/3/4/5/6/7 rev. 1.5 289 23.1.3. mode 2: 8-bit counter/timer with auto-reload mode 2 configures timer 0 and timer 1 to operate as 8-bit counter/timers with automatic reload of the start value. tl0 holds the count and th0 holds the reload va lue. when the counter in tl0 overflows from 0xff to 0x00, the timer overflow flag tf 0 (tcon.5) is set and the counter in tl0 is reloaded from th0. if timer 0 interrupts are enabled, an interrupt will occur when the tf0 flag is set. the reload value in th0 is not changed. tl0 must be initialized to the desired value before enabling the timer for the first count to be cor- rect. when in mode 2, timer 1 operates identically to timer 0. both counter/timers are enabled and configured in mode 2 in the same manner as mode 0. setting the tr0 bit (tcon.4) enables the timer when either gate0 (tmod.3) is logic 0 or when the input signal /int0 is low. figure 23.2. t0 mode 2 block diagram tclk tmod t 1 m 1 t 1 m 0 c / t 1 g a t e 1 g a t e 0 c / t 0 t 0 m 1 t 0 m 0 tcon tf0 tr0 tr1 tf1 ie1 it1 ie0 it0 interrupt tl0 (8 bits) reload th0 (8 bits) 0 1 0 1 sysclk pre-scaled clock ckcon s c a 0 s c a 1 t 1 m t 0 m tr0 gate0 /int0 t0 crossbar c8051f040/1/2/3/4/5/6/7 290 rev. 1.5 23.1.4. mode 3: two 8-bit counter/timers (timer 0 only) in mode 3, timer 0 is configured as two separate 8-bit counter/timers held in tl0 and th0. the counter/ timer in tl0 is controlled using the timer 0 control/status bits in tcon and tmod: tr0, c/t0, gate0 and tf0. tl0 can use ei ther the system clock or an external input si gnal as its timebase. the th0 register is restricted to a timer function sourced by the system clock or prescaled clock. th0 is enabled using the timer 1 run control bit tr1. th0 sets the timer 1 over flow flag tf1 on overflow and thus controls the timer 1 interrupt. timer 1 is inactive in mode 3. when timer 0 is operat ing in mode 3, timer 1 can be operated in modes 0, 1 or 2, but cannot be clocked by external signals nor set the tf1 flag and generate an interrupt. however, the timer 1 overflow can be used to generate baud ra tes for the smbus and/or ua rt, and/or initiate adc conversions. while timer 0 is operating in mode 3, timer 1 run control is handled through its mode set- tings. to run timer 1 while timer 0 is in mode 3, set the timer 1 mode as 0, 1, or 2. to disable timer 1, configure it for mode 3. figure 23.3. t0 mode 3 block diagram tl0 (8 bits) tmod 0 1 tcon tf0 tr0 tr1 tf1 ie1 it1 ie0 it0 interrupt interrupt 0 1 sysclk pre-scaled clock tr1 th0 (8 bits) ckcon s c a 0 s c a 1 t 1 m t 0 m t 1 m 1 t 1 m 0 c / t 1 g a t e 1 g a t e 0 c / t 0 t 0 m 1 t 0 m 0 tr0 gate0 /int0 t0 crossbar c8051f040/1/2/3/4/5/6/7 rev. 1.5 291 sfr definition 23.1. tcon: timer control bit7: tf1: timer 1 overflow flag. set by hardware when timer 1 overflows. this flag can be cleared by software but is auto- matically cleared when the cpu vectors to the timer 1 interrupt service routine. 0: no timer 1 overflow detected. 1: timer 1 has overflowed. bit6: tr1: timer 1 run control. 0: timer 1 disabled. 1: timer 1 enabled. bit5: tf0: timer 0 overflow flag. set by hardware when timer 0 overflows. this flag can be cleared by software but is auto- matically cleared when the cpu vectors to the timer 0 interrupt service routine. 0: no timer 0 overflow detected. 1: timer 0 has overflowed. bit4: tr0: timer 0 run control. 0: timer 0 disabled. 1: timer 0 enabled. bit3: ie1: external interrupt 1. this flag is set by hardware when an edge/level of type defined by it1 is detected. it can be cleared by software but is automatically cleared when the cpu vectors to the external inter- rupt 1 service routine if it1 = 1. this flag is the inverse of the /int1 signal. bit2: it1: interrupt 1 type select. this bit selects whether t he configured /int1 interrupt will be falling-edge sensitive or active-low. 0: /int1 is level triggered, active-low. 1: /int1 is edge tr iggered, falling-edge. bit1: ie0: external interrupt 0. this flag is set by hardware when an edge/level of type defined by it0 is detected. it can be cleared by software but is automatically cleared when the cpu vectors to the external inter- rupt 0 service routine if it0 = 1. this flag is the inverse of the /int0 signal. bit0: it0: interrupt 0 type select. this bit selects whether t he configured /int0 interrupt will be falling-edge sensitive or active-low. 0: /int0 is level trigge red, active logic-low. 1: /int0 is edge tr iggered, falling-edge. r/w r/w r/w r/w r/w r/w r/w r/w reset value tf1 tr1 tf0 tr0 ie1 it1 ie0 it0 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 bit addressable sfr address: sfr page: 0x88 0 c8051f040/1/2/3/4/5/6/7 292 rev. 1.5 sfr definition 23.2. tmod: timer mode bit7: gate1: timer 1 gate control. 0: timer 1 enabled when tr1 = 1 irrespective of /int1 logic level. 1: timer 1 enabled only when tr1 = 1 and /int1 = logic 1. bit6: c/t1: counter/timer 1 select. 0: timer function: timer 1 incremented by clock defined by t1m bit (ckcon.4). 1: counter function: timer 1 incremented by high-to-low transitions on external input pin (t1). bits5-4: t1m1-t1m0: timer 1 mode select. these bits select the timer 1 operation mode. bit3: gate0: timer 0 gate control. 0: timer 0 enabled when tr0 = 1 irrespective of /int0 logic level. 1: timer 0 enabled only when tr0 = 1 and /int0 = logic 1. bit2: c/t0: counter/timer select. 0: timer function: timer 0 incremented by clock defined by t0m bit (ckcon.3). 1: counter function: timer 0 incremented by high-to-low transitions on external input pin (t0). bits1-0: t0m1-t0m0: timer 0 mode select. these bits select the timer 0 operation mode. r/w r/w r/w r/w r/w r/w r/w r/w reset value gate1 c/t1 t1m1 t1m0 gate0 c/t0 t0m1 t0m0 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: sfr page: 0x89 0 t1m1 t1m0 mode 0 0 mode 0: 13-bit counter/timer 0 1 mode 1: 16-bit counter/timer 1 0 mode 2: 8-bit counter/timer with auto-reload 1 1 mode 3: timer 1 inactive t0m1 t0m0 mode 0 0 mode 0: 13-bit counter/timer 0 1 mode 1: 16-bit counter/timer 1 0 mode 2: 8-bit counter/timer with auto-reload 1 1 mode 3: two 8-bit counter/timers c8051f040/1/2/3/4/5/6/7 rev. 1.5 293 sfr definition 23.3. ckcon: clock control sfr definition 23.4. tl0: timer 0 low byte bits7-5: unused. read = 000b, write = don?t care. bit4: t1m: timer 1 clock select. this select the clock source su pplied to timer 1. t1m is ignore d when c/t1 is set to logic 1. 0: timer 1 uses the clock defined by the prescale bits, sca1-sca0. 1: timer 1 uses the system clock. bit3: t0m: timer 0 clock select. this bit selects the clock source supplied to timer 0. t0m is ignored when c/t0 is set to logic 1. 0: counter/timer 0 uses the clock defined by the prescale bits, sca1-sca0. 1: counter/timer 0 uses the system clock. bit2: unused. read = 0b, write = don?t care. bits1-0: sca1-sca0: ti mer 0/1 prescale bits these bits control the division of the clock su pplied to timer 0 and/or timer 1 if configured to use prescaled clock inputs. r/w r/w r/w r/w r/w r/w r/w r/w reset value - - - t1m t0m - sca1 sca0 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: sfr page: 0x8e 0 sca1 sca0 prescaled clock 0 0 system clock divided by 12 0 1 system clock divided by 4 1 0 system clock divided by 48 1 1 external clock divided by 8 bits 7-0: tl0: timer 0 low byte. the tl0 register is the low byte of the 16-bit timer 0. r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: sfr page: 0x8a 0 c8051f040/1/2/3/4/5/6/7 294 rev. 1.5 sfr definition 23.5. tl1: timer 1 low byte sfr definition 23.6. th0: timer 0 high byte sfr definition 23.7. th1: timer 1 high byte bits 7-0: tl1: timer 1 low byte. the tl1 register is the low byte of the 16-bit timer 1. r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: sfr page: 0x8b 0 bits 7-0: th0: timer 0 high byte. the th0 register is the high byte of the 16-bit timer 0. r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: sfr page: 0x8c 0 bits 7-0: th1: timer 1 high byte. the th1 register is the high byte of the 16-bit timer 1. r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: sfr page: 0x8d 0 c8051f040/1/2/3/4/5/6/7 rev. 1.5 295 23.2. timer 2, timer 3, and timer 4 timers n are 16-bit counter/timers, each formed by two 8-bit sfrs: tmrnl (low byte) and tmrnh (high byte) where n = 2, 3, and 4 for timers 2, 3, and 4 re spectively. these timers feature auto-reload, capture, and toggle output modes with the ab ility to count up or down. captur e mode and auto-r eload mode are selected using bits in the timer n control registers (tmrncn). toggle output mode is selected using the timer 2, 3, and 4 configuration registers (tmrncf). these timers may also be used to generate a square- wave at an external pin. as with timers 0 and 1, timers n can use either the system clock (divided by one, two, or twelve), external clock (divid ed by eight) or transitions on an ex ternal input pin as its clock source. the counter/timer select bit c/tn (tmrncn.1) configures the peripheral as a counter or timer. clearing c/tn configures the timer to be in a timer mode (i.e., the system clock or extern al clock as input for the timer). when c/tn is set to 1, the timer is configured as a counter (i.e ., high-to-low transitions at the tn input pin increment (or decrement) the counter/timer register). refer to section ?17.1. ports 0 through 3 and the priority crossbar decoder? on page 204 for information on selecting and configuring external i/ o pins for digital peripherals, such as the tn pin. timer 2 and 3 can be used to start an adc data conver- sion and timers 2, 3, and 4 can schedule dac output s. only timer 1 can be used to generate baud rates for uart 1, and timers 1, 2, 3, or 4 may be used to generate baud rates for uart 0. timer n can use either sysclk, sysclk divided by 2, sysclk divided by 12, an external clock divided by 8, or high-to-low transitions on the tn input pin as its clock source when operating in counter/timer with capture mode. clearing the c/tn bit (tmrncn.1) selects the system clock/external clock as the input for the timer. the timer clock select bits tnm0 and tnm1 in tmrncf can be used to select the system clock undivided, system clock divided by two, system clock di vided by 12, or an external clock provided at the xtal1/xtal2 pins divided by 8 (see sfr definition 23.9 ). when c/tn is set to logic 1, a high-to-low tran- sition at the tn input pin increments the counter /timer register (i.e., conf igured as a counter). 23.2.1. configuring timer 2, 3, and 4 to count down timers 2, 3, and 4 have the abilit y to count down. when the timer?s respective decrement enable bit (dcen) in the timer configuration regi ster (see sfr definition 23.9) is set to ?1?, the timer can then count up or down . when dcen = 1, the direction of the timer?s co unt is controlled by the tnex pin?s logic level. when tnex = 1, the counter/timer will count up; when tnex = 0, the coun ter/timer will count down. to use this feature, tnex must be enabled in the digital crossbar and configured as a digital input. note: when dcen = 1, other functions of the tnex inpu t (i.e., capture and auto-reload) are not available. tnex will only control the direction of the timer when dcen = 1. c8051f040/1/2/3/4/5/6/7 296 rev. 1.5 23.2.2. capture mode in capture mode, time r n will operate as a 16-bit counter/timer with ca pture facility. when the timer exter- nal enable bit (found in the tmrncn register) is set to ?1?, a high-to-low transition on the tnex input pin causes the 16-bit value in the associated timer (tmrnh, tmrnl) to be loaded into the capture registers (rcapnh, rcapnl). if a capture is triggered in the counter/timer, the timer external flag (tmrncn.6) will be set to ?1? and an interrupt will o ccur if the interrupt is enabled. see section ?12.3. interrupt han- dler? on page 153 for further information concerning t he configuration of interrupt sources. as the 16-bit timer register increments and overfl ows tmrnh:tmrnl, the tfn timer overflow/underflow flag (tmrncn.7) is set to ?1? and an interrupt will occur if t he interrupt is enabled. th e timer can be config- ured to count down by se tting the decrement enable bit (tmrncf.0) to ?1?. this will cause the timer to decrement with every timer clock/count event and underflow when the timer transitions from 0x0000 to 0xffff. just as in overflows, the overflow/underflow flag (tfn) will be set to ?1?, and an interrupt will occur if enabled. counter/timer with capture mode is selected by setting the capture/reload select bit cp/rln (tmrncn.0) and the timer n run control bit trn (tmrncn.2) to logic 1. the timer n respective external enable exenn (tmrncn.3) must also be set to logic 1 to enable capt ures. if exenn is cleared, transi- tions on tnex will be ignored. figure 23.4. tn capture mode block diagram tmrnl tmrnh trn tclk interrupt tmrncn exfn exenn trn c/tn cp/rln tfn sysclk 12 2 tmrncf d c e n t n o e t o g n t n m 1 t n m 0 toggle logic tn (port pin) 0 1 1 0 exenn crossbar tne x rcapnl rcapnh 0xff 0xff 8 external clock (xtal1) tn crossbar c8051f040/1/2/3/4/5/6/7 rev. 1.5 297 23.2.3. auto-reload mode in auto-reload mode, the counter/timer can be configured to count up or down and cause an interrupt/flag to occur upon an overflow/underflow event. when counting up, the coun ter/timer will set its overflow/under- flow flag (tfn) and cause an interrupt (if enabled) upon overflow/underflow, the values in the reload/cap- ture registers (rcapnh and rcapnl) are loaded into the timer, and the timer is restarted. when the timer external enable bit ( exenn) bit is set to ?1? and the decrement enable bit (dce n) is ?0?, a ?1?-to-?0? transition on the tnex pin (configured as an input in the digital crossbar ) will cause a timer reload (in addi- tion to timer overflows causing auto-reloads). when dcen is set to ?1?, the state of the tnex pin controls whether the counter/timer counts up (increments) or down (decrements), and will no t cause an auto-reload or interrupt event. see section 23.2.1 for information concerning configuration of a timer to count down. when counting down, the c ounter/timer will set its overflow/underflow flag (tfn) and cause an interrupt (if enabled) when the value in the timer (tmrnh and tm rnl registers) matches the 16-bit value in the reload/capture registers (rcapnh an d rcapnl). this is considered an underflow event, and will cause the timer to load the value 0xffff. the timer is automatically restarted wh en an underflow occurs. counter/timer with auto-reload mode is selected by clearing the cp/rln bit. setting trn to logic 1 enables and starts the timer. in auto-reload mode, the external flag (exfn) togg les upon every overflow or underflow and does not cause an interrupt. the exfn flag can be thought of as the most significant bit (msb) of a 17-bit counter. figure 23.5. tn auto-reload mode and toggle mode block diagram tmrnl tmrnh trn tclk reload interrupt exenn crossbar tne x tmrncn exfn exenn trn c/tn cp/rln tfn sysclk 12 2 tmrncf d e c e n t n o e t o g n t n m 1 t n m 0 toggle logic tn (port pin) 0 1 1 0 rcapnl rcapnh 0xff 0xff ovf 8 external clock (xtal1) tn crossbar c8051f040/1/2/3/4/5/6/7 298 rev. 1.5 23.2.4. toggle output mode timer n have the capability to toggle the state of their respective output port pins (t2, t3, or t4) to produce a 50% duty cycle waveform output. the port pin state will change up on the overflow or underflow of the respective timer (depending on whether the timer is counting up or down ). the toggle frequency is deter- mined by the clock source of the timer and the values loaded into rcapnh and rcapnl. when counting down, the auto-reload value for the timer is 0xffff, and underflow will occur when the value in the timer matches the value stored in rcapnh:rcapnl. when co unting up, the auto-reload value for the timer is rcapnh:rcapnl, and overflow will occur when the va lue in the timer transi tions from 0xffff to the reload value. to output a square wave, the timer is placed in re load mode (the capture/re load select bit in tmrncn and the timer/counter select bit in tmrncn are cleared to ?0?). the timer output is enabled by setting the timer output enable bit in tmrncf to ?1?. the time r should be configured via the timer clock source and reload/underflow values such that the timer overflow/u nderflows at 1/2 the desire d output frequency. the port pin assigned by the crossbar as the timer?s output pin should be configured as a digital output (see section ?17. port input/output? on page 203 ). setting the timer?s run bit (trn) to ?1? will start the toggle of the pin. a read/write of the timer?s toggle output state bit (tmrncf.2) is used to read the state of the toggle output, or to force a value of the output. this is useful when it is desired to start the toggle of a pin in a known state, or to force the pin into a desired state when the toggle mode is halted. equation 23.1. square wave frequency equation 23.1 applies regardless of whether t he timer is configured to count up or down. f sq f tclk 265536 rcapn ? ?? ? c8051f040/1/2/3/4/5/6/7 rev. 1.5 299 sfr definition 23.8. tmrncn: timer n control bit7: tfn: timer n overflow/underflow flag. set by hardware when either the timer overfl ows from 0xffff to 0x0000, underflows from the value placed in rcapnh:rcapnl to 0xffff (in auto-reload mode), or underflows from 0x0000 to 0xffff (in capture mode). when the timer interrupt is enabled, setting this bit causes the cpu to vector to the timer interrupt service rout ine. this bit is not automatically cleared by hardware and must be cleared by software. bit6: exfn: timer 2, 3, or 4 external flag. set by hardware when either a capture or rel oad is caused by a high-to-low transition on the tnex input pin and exenn is logic 1. when the timer interrupt is enabled, sett ing this bit causes the cpu to vector to the timer interrupt service routine. this bi t is not automatically cleared by hardware and must be cleared by software. bit5-4: reserved. bit3: exenn: timer n external enable. enables high-to-low transitions on tnex to trigger captures, reloads, and control the direc- tion of the timer/coun ter (up or down count). if decen = 1, tnex will determ ine if the timer counts up or down when in auto-reload mode. if exenn = 1, tn ex should be configured as a digital input. 0: transitions on the tnex pin are ignored. 1: transitions on the tnex pin cause capture, re load, or control the direction of timer count (up or down) as follows: capture mode : ?1?-to-?0? transition on tnex pin ca uses rcapnh:rcapnl to capture timer value. auto-reload mode : dcen = 0: ?1?-to-?0? transition causes reload of timer and sets the exfn flag. dcen = 1: tnex logic level controls direction of timer (up or down). bit2: trn: timer n run control. this bit enables/disables the respective timer. 0: timer disabled. 1: timer enabled and running/counting. bit1: c/tn: counter/timer select. 0: timer function: timer incremented by clock defined by tnm1:tnm0 (tmrncf.4:tmrncf.3). 1: counter function: timer incremented by hi gh-to-low transitions on external input pin. bit0: cp/rln: capture/reload select. this bit selects whether the timer functions in capture or auto-reload mode. 0: timer is in auto-reload mode. 1: timer is in capture mode. r/w r/w r/w r/w r/w r/w r/w r/w reset value tfn exfn - - exenn trn c/tn cp/rln 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 bit addressable sfr address: tmr2cn:0xc8;tmr3cn:0xc8;tmr4cn:0xc8 sfr page: tmr2cn: page 0;tmr3cn: page 1;tmr4cn: page 2 c8051f040/1/2/3/4/5/6/7 300 rev. 1.5 sfr definition 23.9. tmrncf: timer n configuration bit7-5: reserved. bit4-3: tnm1 and tnm0: timer clock mode select bits. bits used to select the timer clock sour ce. the sources can be the system clock (sysclk), sysclk divided by 2 or 12, or an exte rnal clock signal rout ed to tn (port pin) divided by 8. clock source is selected as follows: 00: sysclk/12 01: sysclk 10: external clock/8 11: sysclk/2 bit2: togn: toggle output state bit. when timer is used to toggle a port pin, this bi t can be used to read the state of the output, or can be written to in order to force the state of the output. bit1: tnoe: timer output enable bit. this bit enables the timer to output a 50% duty cycle output to the timer?s assigned external port pin. note : a timer is configured for square wave output as follows: cp/rln = 0 c/tn = 0 tnoe = 1 load rcapnh:rcapnl (see section ?equation 23.1. square wave frequency? on page 298 ). configure port pin for output (see section ?17. port input/output? on page 203 ). 0: output of toggle mode not available at timers? assigned port pin. 1: output of toggle mode available at timers? assigned port pin. bit0: dcen: decrement enable bit. this bit enables the timer to count up or down as determined by the state of tnex. 0: timer will count up, regardless of the state of tnex. 1: timer will count up or down dependin g on the state of tnex as follows: if tnex = 0, the timer counts down if tnex = 1, the timer counts up. r/w r/w r/w r/w r/w reset value - - - tnm1 tnm0 togn tnoe dcen 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 bit addressable sfr address: tmr2cf:0xc9;tmr3cf:0xc9;tmr4cf:0xc9 sfr page tmr2cf: page 0;tmr3cf: page 1;tmr4cf: page 2 c8051f040/1/2/3/4/5/6/7 rev. 1.5 301 sfr definition 23.10. rcapnl: timer n captur e register low byte sfr definition 23.11. rcapnh: timer n captur e register hig h byte sfr definition 23.12. tmrnl: timer n low byte bits 7-0: rcapnl: timer n capture register low byte. the rcapnl register captures the low byte of timer n when timer n is configured in capture mode. when timer n is configured in auto-reload mode, it holds the low byte of the reload value. r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: rcap2l: 0xca; rcap3l: 0xca; rcap4l: 0xca sfr page: rcap2l: page 0; rcap3l: page 1; rcap4l: page 2 bits 7-0: rcapnh: timer n capture register high byte. the rcapnh register captures the high byte of timer n when timer n is configured in cap- ture mode. when timer n is configured in auto -reload mode, it holds the high byte of the reload value. r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: rcap2h: 0xcb; rcap3h: 0xcb; rcap4h: 0xcb sfr page: rcap2h: page 0; rcap3h: page 1; rcap4h: page 2 bits 7-0: tmrnl: timer n low byte. the tmrnl register contains the low byte of the 16-bit timer n r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: tmr2l: 0xcc; tmr3l: 0xcc; tmr4l: 0xcc sfr page: tmr2l: page 0; tmr3l: page 1; tmr4l: page 2 c8051f040/1/2/3/4/5/6/7 302 rev. 1.5 sfr definition 23.13. tmrnh timer n high byte bits 7-0: tmrnh: timer n high byte. the tmrnh register contains the high byte of the 16-bit timer n r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: tmr2h: 0xcd; tmr3h: 0xcd; tmr4h: 0xcd sfr page: tmr2h: page 0; tmr3h: page 1; tmr4h: page 2 c8051f040/1/2/3/4/5/6/7 rev. 1.5 303 24. programmable counter array the programmable counter array (pca0) provides enhanced timer functionality while requiring less cpu intervention than the standard 8051 counter/timers. pc a0 consists of a dedicated 16-bit counter/timer and six 16-bit capture/compare modules. each capture/compare module has its own associated i/o line (cexn) which is routed through the crossbar to port i/o when enabled (see section ?17.1. ports 0 through 3 and the priority crossbar decoder? on page 204 ). the counter/timer is driven by a program- mable timebase that can select between six inputs as its source: system clock, system clock divided by four, system clock divided by twelve, the external oscilla tor clock source divided by 8, timer 0 overflow, or an external clock signal on the eci line. each capture/compare module may be configured to operate inde- pendently in one of six modes: edge-triggered ca pture, software timer, high-speed output, frequency output, 8-bit pwm, or 16-bit pwm (each is described in section 24.2 ). the pca is configured and con- trolled through the system controller's special function registers. the basic pca block diagram is shown in figure 24.1. figure 24.1. pca block diagram capture/compare module 1 capture/compare module 0 capture/compare module 2 capture/compare module 3 cex1 eci crossbar cex2 cex3 cex0 port i/o 16-bit counter/timer pca clock mux sysclk/12 sysclk/4 timer 0 overflow eci sysclk external clock/8 capture/compare module 4 cex4 capture/compare module 5 cex5 c8051f040/1/2/3/4/5/6/7 304 rev. 1.5 24.1. pca counter/timer the 16-bit pca counter/timer consists of two 8-bi t sfrs: pca0l and pca0h. pca0h is the high byte (msb) of the 16-bit counter/timer and pca0l is the lo w byte (lsb). reading pc a0l automatically latches the value of pca0h into a ?snapshot? register; the following pca0h read accesses this ?snapshot? register. reading the pca0l register first guarantees an accu rate reading of the entire 16-bit pca0 counter. reading pca0h or pca0l does not disturb the counte r operation. the cps2-cps0 bits in the pca0md register select the timebase for the counter/timer as shown in table 24.1. note that in ?external oscillator source divided by 8? mode, the external oscillator source is synchr onized with the system clock, and must have a frequency less than or equal to the system clock. when the counter/timer overflows from 0xffff to 0x0 000, the counter overflow fl ag (cf) in pca0md is set to logic 1 and an interrupt request is generated if cf interrupts are enabled. setting the ecf bit in pca0md to logic 1 enables the cf flag to generate an interrupt request. the cf bit is not automatically cleared by hardware when the cpu vectors to the inte rrupt service routine, and must be cleared by soft- ware (note: pca0 interrupts must be globally enabled before cf interrupts are recognized. pca0 inter- rupts are globally enabled by setting the ea bit (ie.7) and the epca0 bit in eie1 to logic 1). clearing the cidl bit in the pca0md register a llows the pca to continue normal op eration while the cpu is in idle mode. figure 24.2. pca counter /timer block diagram table 24.1. pca timebase input options cps2 cps1 cps0 timebase 0 0 0 system clock divided by 12 0 0 1 system clock divided by 4 0 1 0 timer 0 overflow 011 high-to-low transitions on eci 1 (max rate = system clock divided by 4) 100system clock 101 external clock divided by 8 2 notes: 1. the m inimum high or lo w time for the eci input signal is at least 2 system clock cycles. 2. exter nal oscillator source divided by 8 is synchronized with the system clock. pca0md c i d l w d t e e c f c p s 1 c p s 0 w d l c k c p s 2 idle 0 1 pca0h pca0l snapshot register to sfr bus overflow to pca interrupt system cf pca0l read to pca modules sysclk/12 sysclk/4 timer 0 overflow eci 000 001 010 011 100 101 sysclk external clock/8 pca0cn c f c r c c f 0 c c f 2 c c f 1 c c f 5 c c f 4 c c f 3 c8051f040/1/2/3/4/5/6/7 rev. 1.5 305 24.2. capture/compare modules each module can be configured to operate independently in one of six operation modes: edge-triggered capture, software timer, high speed output, frequency output, 8-bit pulse width modulator, or 16-bit pulse width modulator. each module has special func tion registers (sfrs) asso ciated with it in the cip- 51 system controller. these registers are used to exchange data with a module and configure the module's mode of operation. table 24.2 summarizes the bit settings in the pca0cp mn registers used to select the pca0 capture/com- pare module?s operating modes. setting the eccfn bi t in a pca0cpmn register enables the module's ccfn interrupt. note: pca0 interrupts must be globally enabled before individual ccfn interrupts are rec- ognized. pca0 interrupts are globally enabled by sett ing the ea bit (ie.7) and the epca0 bit (eie1.3) to logic 1. see figure 24.3 for details on the pca interrupt configuration. figure 24.3. pca interrupt block diagram table 24.2. pca0cpm register settings fo r pca capture/comp are modules pwm16 ecom capp capn mat tog pwm eccf operation mode x x 10000x capture triggered by positive edge on cexn x x 01000x capture triggered by negative edge on cexn x x 11000xcapture triggered by transition on cexn x 1 00100x software timer x 1 00110x high-speed output x 1 00011x frequency output 0 1 000010 8-bit pulse width modulator 1 1 000010 16-bit pulse width modulator x = don?t care pca0cn c f c r c c f 0 c c f 2 c c f 1 c c f 5 c c f 4 c c f 3 pca0md c i d l e c f c p s 1 c p s 0 c p s 2 0 1 pca module 0 ccf0 pca module 1 ccf1 eccf1 0 1 eccf0 0 1 pca module 2 ccf2 eccf2 0 1 pca module 3 ccf3 eccf3 eccf4 pca counter/ timer overflow 0 1 interrupt priority decoder epca0 (eie1.3) pca0cpmn (for n = 0 to 5) p w m 1 6 n e c o m n e c c f n t o g n p w m n c a p p n c a p n n m a t n 0 1 pca module 4 ccf4 0 1 pca module 5 ccf5 0 1 ea (ie.7) 0 1 eccf5 c8051f040/1/2/3/4/5/6/7 306 rev. 1.5 24.2.1. edge-triggered capture mode in this mode, a valid transition on the cexn pin caus es pca0 to capture the value of the pca0 counter/ timer and load it into the corresponding module's 16-bit capture/compare register (pca0cpln and pca0cphn). the cappn and capnn bits in the pca0cpmn register are used to select the type of transi- tion that triggers the capture: low-to-high transition (p ositive edge), high-to-low transition (negative edge), or either transition (positive or negative edge). when a capture occurs, the capture/compare flag (ccfn) in pca0cn is set to logic 1 and an interrupt request is generated if ccf interrupts are enabled. the ccfn bit is not automatically cleared by hardware when th e cpu vectors to the interrupt service routine, and must be cleared by software. note : the signal at the cexn pin must be logic high or low for at least two system clock cycles in order for it to be recognized as valid by the hardware. figure 24.4. pca capture mode diagram pca0l pca0cpln pca timebase cexn crossbar port i/o pca0h capture pca0cphn 0 1 0 1 (to ccfn) pca interrupt pca0cpmn p w m 1 6 n e c o m n e c c f n t o g n p w m n c a p p n c a p n n m a t n pca0cn c f c r c c f 0 c c f 2 c c f 1 c c f 5 c c f 4 c c f 3 c8051f040/1/2/3/4/5/6/7 rev. 1.5 307 24.2.2. software timer (compare) mode in software timer mode, the pca0 counter/timer is compared to the module's 16-bit capture/compare reg- ister (pca0cphn and pca0cpln). when a match oc curs, the capture/compare flag (ccfn) in pca0cn is set to logic 1 and an interrupt request is generated if ccf interrupts are enabled. the ccfn bit is not automatically cleared by hardware when the cpu vect ors to the interrupt service routine, and must be cleared by software. setting the ecomn and matn bits in the pca0cpmn register enables software timer mode. important note about capture/compare registers: when writing a 16-bit value to the pca0 capture/ compare registers, the low byte should always be wri tten first. writing to pca0cpln clears the ecomn bit to '0'; writing to pca0 cphn sets ecomn to '1'. figure 24.5. pca software timer mode diagram match 16-bit comparator pca0h pca0cphn enable pca0l pca timebase pca0cpln 00 00 pca interrupt 0 1 x enb enb 0 1 write to pca0cpln write to pca0cphn reset pca0cpmn p w m 1 6 n e c o m n e c c f n t o g n p w m n c a p p n c a p n n m a t n x pca0cn c f c r c c f 0 c c f 2 c c f 1 c c f 5 c c f 4 c c f 3 c8051f040/1/2/3/4/5/6/7 308 rev. 1.5 24.2.3. high-speed output mode in high-speed output mode, a module?s associated cexn pin is toggled each time a match occurs between the pca counter and the module's 16- bit capture/compare register (pca0cphn and pca0cpln). setting the togn, matn, and ecomn bits in the pca0cpmn register enables the high- speed output mode. important note about capture/compare registers: when writing a 16-bit value to the pca0 capture/ compare registers, the low byte should always be wri tten first. writing to pca0cpln clears the ecomn bit to '0'; writing to pca0 cphn sets ecomn to '1'. figure 24.6. pca high-spee d output mode diagram match 16-bit comparator pca0h pca0cphn enable pca0l pca timebase pca0cpln pca interrupt 0 1 00 0x enb enb 0 1 write to pca0cpln write to pca0cphn reset pca0cpmn p w m 1 6 n e c o m n e c c f n t o g n p w m n c a p p n c a p n n m a t n x cexn crossbar port i/o toggle 0 1 togn pca0cn c f c r c c f 0 c c f 2 c c f 1 c c f 5 c c f 4 c c f 3 c8051f040/1/2/3/4/5/6/7 rev. 1.5 309 24.2.4. frequency output mode frequency output mode produces a programmable-freq uency square wave on the module?s associated cexn pin. the capture/compare module high byte holds the number of pca clocks to count before the out- put is toggled. the frequency of the square wave is then defined by equation 24.1, where f pca is the fre- quency of the clock selected by the cps2 -0 bits in the pca mode register, pca0md. note: a value of 0x00 in the pca0cphn regi ster is equal to 256 for this equation. the lower byte of the capture/compare module is co mpared to the pca0 counter low byte; on a match, cexn is toggled and the offset held in the high byte is added to the matched value in pca0cpln. fre- quency output mode is enabled by setting the ecom n, togn, and pwmn bits in the pca0cpmn register. figure 24.7. pca frequency output mode equation 24.1. square wave frequency output f sqr f pca 2 pca0 cphn ? 8-bit comparator pca0l enable pca timebase 000 0 match pca0cpmn p w m 1 6 n e c o m n e c c f n t o g n p w m n c a p p n c a p n n m a t n 0 pca0cphn 8-bit adder pca0cpln adder enable cexn crossbar port i/o toggle 0 1 togn 1 c8051f040/1/2/3/4/5/6/7 310 rev. 1.5 24.2.5. 8-bit pulse width modulator mode each module can be used independently to generate pulse width modulated (pwm) outputs on its associ- ated cexn pin. the frequency of th e output is dependent on the timebase for the pca0 counter/timer. the duty cycle of the pwm output signal is varied using the module's pca0cpln capture/compare register. when the value in the low byte of the pca0 counter /timer (pca0l) is equal to the value in pca0cpln, the output on the cexn pin will be high . when the count value in pca0l ov erflows, the cexn output will be low (see figure 24.8). also, when the counter/timer low byte (pca0l) overflows from 0xff to 0x00, pca0cpln is reloaded automatically with the value stor ed in the counter/timer's high byte (pca0h) with- out software intervention. setting the ecomn and pw mn bits in the pca0cpmn register enables 8-bit pulse width modulator mode. the duty cycle for 8-bit pwm mode is given by equation 24.2. important note about capture/compare registers: when writing a 16-bit value to the pca0 capture/ compare registers, the low byte should always be wri tten first. writing to pca0cpln clears the ecomn bit to '0'; writing to pca0 cphn sets ecomn to '1'. equation 24.2. 8-bit pwm duty cycle figure 24.8. pca 8-bi t pw m mode diagram dutycycle 256 pca0 cphn ? ?? 256 ----------------------------------- ---------------- = 8-bit comparator pca0l pca0cpln pca0cphn cexn crossbar port i/o enable overflow pca timebase 0000 0 q q set clr s r match pca0cpmn p w m 1 6 n e c o m n e c c f n t o g n p w m n c a p p n c a p n n m a t n 0 c8051f040/1/2/3/4/5/6/7 rev. 1.5 311 24.2.6. 16-bit pulse width modulator mode each pca0 module may also be operated in 16-bit pwm mode. in this mode, the 16-bit capture/compare module defines the number of pca0 clocks for the lo w time of the pwm signal. when the pca0 counter matches the module contents, the output on cexn is as serted high; when the counter overflows, cexn is asserted low. to output a varying duty cycle, new value writes should be sy nchronized with pca0 ccfn match interrupts. 16-bit pwm mode is enabled by setting the ecomn, pwmn, and pwm16n bits in the pca0cpmn register. for a varying duty cycle, ccfn should also be set to logic 1 to enable match inter- rupts. the duty cycle for 16-bit pwm mode is given by equation 24.3. important note about capture/compare registers: when writing a 16-bit value to the pca0 capture/ compare registers, the low byte should always be wri tten first. writing to pca0cpln clears the ecomn bit to '0'; writing to pca0 cphn sets ecomn to '1'. equation 24.3. 16-bit pwm duty cycle figure 24.9. pca 16-bit pwm mode dutycycle 65536 pca0 cpn ? ?? 65536 ---------------------------------------------------- - = pca0cpln pca0cphn enable pca timebase 0000 0 pca0cpmn p w m 1 6 n e c o m n e c c f n t o g n p w m n c a p p n c a p n n m a t n 1 16-bit comparator cexn crossbar port i/o overflow q q set clr s r match pca0h pca0l c8051f040/1/2/3/4/5/6/7 312 rev. 1.5 24.3. register descriptions for pca0 following are detailed descriptions of the special func tion registers related to the operation of pca0. sfr definition 24.1. pca0cn: pca control bit7: cf: pca counter/timer overflow flag. set by hardware when the pca0 counter/timer overflows from 0xffff to 0x0000. when the counter/timer overflow (cf) interrupt is enabled, setting this bit causes the cpu to vec- tor to the cf interrupt service routine. this bit is not automatically cleared by hardware and must be cleared by software. bit6: cr: pca0 counter /timer run control. this bit enables/disables the pca0 counter/timer. 0: pca0 counter/timer disabled. 1: pca0 counter/timer enabled. bit5: ccf5: pca0 module 5 capture/compare flag. this bit is set by hardware when a match or capture occurs. when the ccf interrupt is enabled, setting this bit causes the cpu to vect or to the ccf interrupt service routine. this bit is not automatically cleared by hard ware and must be cleared by software. bit4: ccf4: pca0 module 4 capture/compare flag. this bit is set by hardware when a match or capture occurs. when the ccf interrupt is enabled, setting this bit causes the cpu to vect or to the ccf interrupt service routine. this bit is not automatically cleared by hard ware and must be cleared by software. bit3: ccf3: pca0 module 3 capture/compare flag. this bit is set by hardware when a match or capture occurs. when the ccf interrupt is enabled, setting this bit causes the cpu to vect or to the ccf interrupt service routine. this bit is not automatically cleared by hard ware and must be cleared by software. bit2: ccf2: pca0 module 2 capture/compare flag. this bit is set by hardware when a match or capture occurs. when the ccf interrupt is enabled, setting this bit causes the cpu to vect or to the ccf interrupt service routine. this bit is not automatically cleared by hard ware and must be cleared by software. bit1: ccf1: pca0 module 1 capture/compare flag. this bit is set by hardware when a match or capture occurs. when the ccf interrupt is enabled, setting this bit causes the cpu to vect or to the ccf interrupt service routine. this bit is not automatically cleared by hard ware and must be cleared by software. bit0: ccf0: pca0 module 0 capture/compare flag. this bit is set by hardware when a match or capture occurs. when the ccf interrupt is enabled, setting this bit causes the cpu to vect or to the ccf interrupt service routine. this bit is not automatically cleared by hard ware and must be cleared by software. r/w r/w r/w r/w r/w r/w r/w r/w reset value cf cr ccf5 ccf4 ccf3 ccf2 ccf1 ccf0 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: sfr page: 0xd8 0 c8051f040/1/2/3/4/5/6/7 rev. 1.5 313 sfr definition 24.2. pca0md: pca0 mode bit7: cidl: pca0 counter/timer idle control. specifies pca0 behavior when cpu is in idle mode. 0: pca0 continues to function normally wh ile the system controlle r is in idle mode. 1: pca0 operation is suspended while the system controller is in idle mode. bits6-4: unused. read = 000b, write = don't care. bits3-1: cps2-cps0: pca0 co unter/timer pulse select. these bits select the timebase source for th e pca0 counter bit0: ecf: pca counter/timer overflow interrupt enable. this bit sets the masking of the pca0 co unter/timer overflow (cf) interrupt. 0: disable the cf interrupt. 1: enable a pca0 counter/timer overflow in terrupt request when cf (pca0cn.7) is set. r/w r/w r/w r/w r/w r/w r/w r/w reset value cidl ? ? ? cps2 cps1 cps0 ecf 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: sfr page: 0xd9 0 cps2 cps1 cps0 timebase 0 0 0 system clock divided by 12 0 0 1 system clock divided by 4 0 1 0 timer 0 overflow 011 high-to-low transitions on eci 1 (max rate = system clock divided by 4) 1 0 0 system clock 101 external clock divided by 8 2 1 1 0 reserved 1 1 1 reserved notes: 1. the minimum high or low time for the eci input signal is at least 2 system clock cycles. 2. external oscillator source divided by 8 is synchr onized with the system clock. c8051f040/1/2/3/4/5/6/7 314 rev. 1.5 sfr definition 24.3. pca0cpmn: pca0 capture/compare mode bit7: pwm16n: 16-bit pulse width modulation enable this bit selects 16-bit mode when pulse width modulation mode is enabled (pwmn = 1). 0: 8-bit pwm selected. 1: 16-bit pwm selected. bit6: ecomn: comparator function enable. this bit enables/disables the compar ator function for pca0 module n. 0: disabled. 1: enabled. bit5: cappn: capture positi ve function enable. this bit enables/disables the positive edge capture for pca0 module n. 0: disabled. 1: enabled. bit4: capnn: capture negative function enable. this bit enables/disables the negative edge capture for pca0 module n. 0: disabled. 1: enabled. bit3: matn: match function enable. this bit enables/disables the match function for pca0 module n. when enabled, matches of the pca0 counter with a module's capture/comp are register cause the ccfn bit in pca0md register to be set to logic 1. 0: disabled. 1: enabled. bit2: togn: toggle function enable. this bit enables/disables the toggle function for pca0 module n. when enabled, matches of the pca0 counter with a module's capture/comp are register cause the logic level on the cexn pin to toggle. if the pwmn bit is also set to logic 1, the module operates in frequency output mode. 0: disabled. 1: enabled. bit1: pwmn: pulse width modulation mode enable. this bit enables/disables the pwm function for pca0 module n. when enabled, a pulse width modulated signal is output on the cexn pin. 8-bit pwm is used if pwm16n is logic 0; 16-bit mode is used if pwm16n logic 1. if the togn bit is also set, the module operates in frequency output mode. 0: disabled. 1: enabled. bit0: eccfn: capture/compare flag interrupt enable. this bit sets the masking of the capture/compare flag (ccfn) interrupt. 0: disable ccfn interrupts. 1: enable a capture/compare flag interrupt request when ccfn is set. r/w r/w r/w r/w r/w r/w r/w r/w reset value pwm16n ecomn cappn capnn matn togn pwmn eccfn 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: pca0cpm0: 0xda, pca0cpm1: 0xdb, pca0cpm2: 0xdc, pca0cpm3: 0xdd, pca0cpm4: 0xde, pca0cpm5: 0xdf sfr page: pca0cpm0: page 0, pca0cpm1: page 0, pca0cpm2: page 0, pca0cpm3: page 0, pca0cpm4: page 0, pca0cpm5: page 0 c8051f040/1/2/3/4/5/6/7 rev. 1.5 315 sfr definition 24.4. pca0l: pca0 counter/timer low byte sfr definition 24.5. pca0h: pca0 counter/timer high byte bits 7-0: pca0l: pca0 counter/timer low byte. the pca0l register holds the low byte (l sb) of the 16-bit pca0 counter/timer. r/wr/wr/wr/wr/wr/wr/w r/wreset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: sfr page: 0xf9 0 bits 7-0: pca0h: pca0 counter/timer high byte. the pca0h register holds the high byte (msb) of the 16-bit pca0 counter/timer. r/wr/wr/wr/wr/wr/wr/w r/wreset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: sfr page: 0xfa 0 c8051f040/1/2/3/4/5/6/7 316 rev. 1.5 sfr definition 24.6. pca0cpln: pca0 capt ure module low byte sfr definition 24.7. pca0cphn: pca0 capture module high byte bits7-0: pca0cpln: pca0 capture module low byte. the pca0cpln register holds the low byte (lsb) of the 16-bit capture module n. r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: pca0cpl0: 0xfb, pca0cpl1: 0xfd, pca0cpl2: 0xe9 , pca0cpl3: 0xeb, pca0cpl4: 0xed, pca0cpl5: 0xe1 sfr page: pca0cpl0: page 0, pca0cpl1: page 0, pca0cpl2: page 0, pca0cpl3: page 0, pca0cpl4: page 0, pca0cpl5: page 0 bits7-0: pca0cphn: pca0 capture module high byte. the pca0cphn register holds the high byte (msb) of the 16-bit capture module n. r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: pca0cph0: 0xfc, pca0cph1: 0xfe, pca0cph2: 0xea, pca0cph3: 0xec, pca0cph4: 0xee, pca0cph5: 0xe2 sfr page: pca0cph0: page 0, pca0cph1: page 0, pca0cph2: page 0, pca0cph3: page 0, pca0cph4: page 0, pca0cph5: page 0 c8051f040/1/2/3/4/5/6/7 rev. 1.5 317 25. jtag (ieee 1149.1) each mcu has an on-chip jtag interface and logic to support boundary scan for production and in-sys- tem testing, flash read/write operations, and non-intru sive in-circuit debug. the jtag interface is fully compliant with the ieee 1149.1 specification. refer to th is specification for detailed descriptions of the test interface and boundary-scan architec ture. access of the jtag instruction register (ir) and data regis- ters (dr) are as described in the test access port and operation of the ieee 1149.1 specification. the jtag interface is accessed via four dedica ted pins on the mcu: tck, tms, tdi, and tdo. through the 16-bit jtag instruction register (ir), any of the seven instructions shown in figure 25.1 can be commanded. there are three drs associated with jtag boundary-scan, and four associated with flash read/write operations on the mcu. jtag register definition 25.1. ir: jtag instruction register reset value 0x0000 bit15 bit0 ir value instruction description 0x0000 extest selects the boundary data register for control and observability of all device pins 0x0002 sample/ preload selects the boundary data register for observability an d presetting the scan-path latches 0x0004 idcode selects device id register (deviceid) 0xffff bypass selects bypass data register 0x0082 flash control selects flashcon register to contro l how the interface logic responds to reads and writes to the flashdat register 0x0083 flash data selects flashdat register for reads and writes to the flash memory 0x0084 flash address selects flashadr register which holds the address of all flash read, write, and erase operations c8051f040/1/2/3/4/5/6/7 318 rev. 1.5 25.1. boundary scan the dr in the boundary scan path is an 134-bit sh ift register. the boundary dr provides control and observability of all the device pins as well as th e sfr bus and weak pullup feature via the extest and sample commands. table 25.1. boundary data regist er bit definitions extest provides access to both capture and updat e actions, while sample only performs a capture. bit action target 0 capture reset enable from mcu update reset enable to /rst pin 1 capture reset input from /rst pin update reset output to /rst pin 2 capture reset enable from mcu update reset enable to /rst pin 3 capture reset input from /rst pin update reset output to /rst pin 4 capture canrx output enable to pin update canrx output enable to pin 5 capture canrx input from pin update canrx output to pin 6 capture cantx output enable to pin update cantx output enable to pin 7 capture cantx input from pin update cantx output to pin 8 capture external clock from xtal1 pin update not used 9 capture weak pullup enable from mcu update weak pullup enable to port pins 10, 12, 14, 16, 18, 20, 22, 24 capture p0.n output enable from mcu (e.g. bit6=p0.0, bit8=p0.1, etc.) update p0.n output enable to pin (e .g. bit6=p0.0oe, bit8=p0.1oe, etc.) 11, 13, 15, 17, 19, 21, 23, 25 capture p0.n input from pin (e.g . bit7=p0.0, bit9=p0.1, etc.) update p0.n output to pin (e.g. bit7=p0.0, bit9=p0.1, etc.) 26, 28, 30, 32, 34, 36, 38, 40 capture p1.n output enable from mcu update p1.n output enable to pin 27, 29, 31, 33, 35, 37, 39, 41 capture p1.n input from pin update p1.n output to pin 42, 44, 46, 48, 50, 52, 54, 56 capture p2.n output enable from mcu update p2.n output enable to pin 43, 45, 47, 49, 51, 53, 55, 57 capture p2.n input from pin update p2.n output to pin 58, 60, 62, 64, 66, 68, 70, 72 capture p3.n output enable from mcu update p3.n output enable to pin 59, 61, 63, 65, 67, 69, 71, 73 capture p3.n input from pin update p3.n output to pin 74, 76, 78, 80, 82, 84, 86, 88 capture p4.n output enable from mcu update p4.n output enable to pin c8051f040/1/2/3/4/5/6/7 rev. 1.5 319 25.1.1. extest instruction the extest instruction is accessed via the ir. the bo undary dr provides contro l and observability of all the device pins as well as the weak pullup feature. all inputs to on-chip logic are set to logic 1. 25.1.2. sample instruction the sample instruction is accessed via the ir. the boundary dr prov ides observability and presetting of the scan-path latches. 25.1.3. bypass instruction the bypass instruction is acce ssed via the ir. it provides access to the standard jtag bypass data reg- ister. 25.1.4. idcode instruction the idcode instruction is accessed via the ir. it provides access to the 32-bit device id register. 75, 77, 79, 81, 83, 85, 87, 89 capture p4.n input from pin update p4.n output to pin 90, 92, 94, 96, 98, 100, 102, 104 capture p5.n output enable from mcu update p5.n output enable to pin 91, 93, 95, 97, 99, 101, 103, 105 capture p5.n input from pin update p5.n output to pin 106, 108, 110, 112, 114, 116, 118, 120 capture p6.n output enable from mcu update p6.n output enable to pin 107, 109, 111, 113, 115, 117, 119, 121 capture p6.n input from pin update p6.n output to pin 122, 124, 126, 128, 130, 132, 134, 136 capture p7.n output enable from mcu update p7.n output enable to pin 123, 125, 127, 129, 131, 133, 135, 137 capture p7.n input from pin update p7.n output to pin table 25.1. boundary data regist er bit definitions (continued) extest provides access to both capture and updat e actions, while sample only performs a capture. bit action target c8051f040/1/2/3/4/5/6/7 320 rev. 1.5 jtag register definition 25.2. deviceid: jtag device id register version = 0000b part number = 0000 0000 0000 0101b (c8051f040/1/2/3/4/5/6/7) manufacturer id = 0010 0100 001 b (silicon labs) reset value version part number manufacturer id 1 0xn0005243 bit31 bit28 bit27 bit12 bit11 bit1 bit0 c8051f040/1/2/3/4/5/6/7 rev. 1.5 321 25.2. flash programming commands the flash memory can be programmed directly over the jtag interface using the flash control, flash data, flash address, and flash scale registers. thes e indirect data registers are accessed via the jtag instruction register. read and write operations on indi rect data registers are performed by first setting the appropriate dr address in the ir register. each read or write is then initiated by writing the appropriate indirect operation code (indopcode) to the selected data register. incoming co mmands to this register have the following format: indopcode: these bit set the operation to pe rform according to the following table: the poll operation is used to check the busy bit as d escribed below. although a capture-dr is performed, no update-dr is allowed for the poll operation. since updates are disabled, polling can be accomplished by shifting in/out a single bit. the read operation initiates a read from the register addressed by the draddress. reads can be initiated by shifting only 2 bits into the indirect register. afte r the read operation is initia ted, polling of the busy bit must be performed to determine when the operation is complete. the write operation initiates a write of writedata to the register addres sed by draddress. registers of any width up to 18 bits can be written. if the register to be written contains fewer than 18 bits, the data in write- data should be left-justified, i.e. its msb should occupy bit 17 above. this allows shorter registers to be written in fewer jtag clock cycles. for example, an 8-bi t register could be written by shifting only 10 bits. after a write is initiated, the busy bit should be polled to determine when the next operation can be initi- ated. the contents of the instruction re gister should not be altered while ei ther a read or write operation is busy. outgoing data from the indirect data register has the following format: the busy bit indicates that the current operation is not com plete. it goes high when an operation is initiated and returns low when complete. read and write commands are ignored while busy is high. in fact, if poll- ing for busy to be low will be followe d by another read or wr ite operation, jtag writes of the next operation can be made while checking for busy to be low. they will be ignored until busy is read low, at which time the new operation will initiate. this bi t is placed ate bit 0 to allow polling by single-bit shifts. when waiting for a read to complete and busy is 0, the following 18 bits can be shifted out to obtain the resulting data. readdata is always right-justified. this allows regi sters shorter than 18 bits to be read using a reduced number of shifts. for example, the results from a byte-read requires 9 bit shifts (busy + 8 bits). 19:18 17:0 indopcode writedata indopcode operation 0x poll 10 read 11 write 19 18:1 0 0 readdata busy c8051f040/1/2/3/4/5/6/7 322 rev. 1.5 jtag register definition 25.3. flashcon: jtag flash control register this register determines how th e flash interface logic will respond to reads and writes to the ? flashdat register. ? bit 7: sfle: scratchpad flash memory access enable when this bit is set, flash reads and writes from user software are directed to the 128-byte scratchpad flash sector. when accessing the scratchpad, flash accesses out of the address range 0x00-0x7f should not be attempte d. reads/writes outside of this range will yield undefined results. 0: flash access is directed to the program/data flash sector. 1: flash access is directed to the 128-byte scratchpad sector. bits6-4: wrmd2-0: write mode select bits. the write mode select bits control how the interface logic responds to writes to the flash- dat register per the following values: 000: a flashdat write replaces the data in the flashdat register, but is otherwise ignored. 001: a flashdat write initiates a write of flashdat into the memory address by the flashadr register. flashadr is incr emented by one when complete. 010: a flashdat write initiates an erasure (sets all bytes to 0xff) of the flash page containing the address in flashadr. the data written must be 0xa5 for the erase to occur. flashadr is not affected. if flashadr targets the read lock byte or the write/erase lock byte, the entire user space will be erased (i.e. entire flash memory except for the reserved area (see section ?15. flash memory? on page 179 ). (all other values for wrmd2-0 are reserved.) bits3-0: rdmd3-0: read mode select bits. the read mode select bits control how the in terface logic responds to reads to the flash- dat register per the following values: 0000: a flashdat read provides the data in the flashdat register, but is otherwise ignored. 0001: a flashdat read initiates a read of the byte addressed by the flashadr regis- ter if no operation is currently active . this mode is used for block reads. 0010: a flashdat read initiates a read of the byte addressed by flashadr only if no operation is active and any data from a previous read has already been read from flashdat. this mode allows si ngle bytes to be read (or the last byte of a block) without initiating an extra read. (all other values for rdmd3-0 are reserved.) reset value sfle wrmd2 wrmd1 wrmd0 rdmd3 rdmd2 rdmd1 rdmd0 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 c8051f040/1/2/3/4/5/6/7 rev. 1.5 323 jtag register definition 25.4. flashdat: jtag flash data jtag register definition 25.5. flashadr: jtag flash address this register is used to read or write data to the flash memory across the jtag interface. bits9-2: data7-0: flash data byte. bit1: fail: flash fail bit. 0: previous flash memory operation was successful. 1: previous flash memory operation failed. us ually indicates the asso ciated memory loca- tion was locked. bit0: busy: flash busy bit. 0: flash interface logic is not busy. 1: flash interface logic is processing a request. reads or writes while busy = 1 will not ? initiate another operation. reset value 0000000000 bit9 bit0 this register holds the address for all jtag flash re ad, write, and erase operations. this register auto- increments after each read or write, regardless of whether the operation succeeded or failed. bits15-0: flash operation 16-bit address. reset value 0x0000 bit15 bit0 c8051f040/1/2/3/4/5/6/7 324 rev. 1.5 25.3. debug support each mcu has on-chip jtag and debug logic that provides non-intrusive, full speed, in-circuit debug sup- port using the prod uction part installed in the end application, via the four pin jtag i/f. silicon labs' debug system supports inspection and modification of memory and registers, breakpoints, and single stepping. no additional target ram, program memory, or communi cations channels are required. all the digital and analog peripherals are functional and work correctly (remain synchr onized) while debugging. the watch- dog timer (wdt) is disabled when the mcu is halted during single stepping or at a breakpoint. the c8051f040dk is a development kit with all the hardware and software necessary to develop applica- tion code and perform in-circuit debug with each mcu in the c8051f04x family. ea ch kit includes an inte- grated development environment (ide) which has a debugger and integrated 8051 assembler. the kit also includes a jtag interface module referred to as the serial adapter. there is also a target application board with a c8051f040 installed. the required cables and wall-mount power supply are also included. c8051f040/1/2/3/4/5/6/7 rev. 1.5 325 d ocument c hange l ist revision 1.4 to revision 1.5 ? high voltage difference amplifier electrical char acteristics tables: corrected common mode rejec - tion ratio min and typ specifications. ? flash memory chapter: corrected text refer ence to ?c8051f12x and c8051f13x?; changed to ?c8051f04x?. ? 10 and 12-bit adc0 track and conversion exampl e t iming figures: corrected bit name text from ?ad0stm? to ?ad0cm?. ? adc0 chapters (10 and 12-bit): updated analog multiplexer figure to represent correct connection of hvre f to ain- in differen tial hvda configuration. ? adc0 chapters (10 and 12-bit): updated hvda section text to clarify usage of hvref pin. ? adc0 chapters (10 and 12-bit): added differential hvda options to amux selection chart table. ? product selection guide table: added rohs-compliant ordering information. ? global dc electrical characteristics table: corr e cted units for ?analog supply current with analog subsystems inactive? to ?a?. ? pin definitions table: corrected hvain- pin descrip tion to ?high voltage dif ference amplifier negative signal input.? ? interrupt summary table: added ?sfrpage? column and sfrpage value for each interrupt source. ? interrupt summary table: co r rected ?t4con? to ?tmr4cn?. ? interrupt summary table: co r rected ?t2con? to ?tmr2cn?. ? interrupt summary table: corr ected ?adwint? to ?ad0wint?. ? sfr memory map table: corrected sfr page for adc2cn from page 1 to page 2. ? oscillators chapter: corrected steps fo r enabling external cryst al oscillator. ? pca0cphn sfr definition: corrected sfr address of pca0cph1 from ?0xfd? to ?0xfe?. c8051f040/1/2/3/4/5/6/7 326 rev. 1.5 c ontact i nformation silicon laboratories inc. 4635 boston lane ? austin, tx 78735 email: mcuinfo@silabs.com ? internet: www.silabs.com silicon laboratories and silicon labs are trademarks of silicon laboratories inc. other products or brandnames mentioned herein are trademark s or registered trademarks of their respective holders the information in this document is believed to be accurate in all respects at the time of publ ication but is subject to change without notice. silicon laboratories assumes no re sponsibility for errors and omissions, and disclaims responsibi lity for any consequen ces resulting from the use of information included herein. additi onally, silicon laborator ies assumes no responsibility for the fun ction- ing of undescribed features or parameters. silicon laboratories reserves the right to make changes without further notice. sili con laboratories makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpos e, nor does silicon laboratories assume any liabi lity arising out of the application or use of any product or circuit, and specifi cally disclaims any and all liability, including without limitation consequential or inciden tal damages. silicon laboratories product s are not designed, intended, or authorized for use in applications in tended to support or sustain life, or for any other application in which the failure of the silicon laboratories product could create a si tuation where personal injury or death may occur. should buyer purchase or use silicon laboratories products for any such unintended or unauthorized ap plication, buyer shall indemnify and hold silicon laboratories harmless against all claims and damages. |
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